Memory cell access circuit
AssigneeInternational Business Machines Corporation
InventorJoseph E. Barth
Life of this patent
Estimating the term…
Abstract
A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors. A second global bitline may be connected to a second one of the plurality of transistors. A secondary sense amplifier may be connected to the first and second global bitlines. A design structure embodied in a machine readable medium used in a design process, includes such a circuit for accessing a memory cell.
Claims8
A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
- a circuit for accessing a memory cell, the circuit comprising:
- a local bitline;
- a local sense amplifier having a plurality of transistors, said local bitline connecting the memory cell to said sense amplifier;
- a first global bitline connected to a first one of said plurality of transistors;
- a second global bitline connected to a second one of said plurality of transistors;
- and
- a secondary sense amplifier connected to said first and second global bitlines.
A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
- a circuit for accessing a memory cell, the circuit comprising:
- a local bitline;
- a first global bitline;
- a second global bitline;
- and
- a local sense amplifier having:
- a first transistor having a gate connected to said local bitline, a source connected to said first global bitline, and a drain connected to said second global bitline;
- a second transistor having a gate connected to said first global bitline, a drain connected to said local bitline, and a source connected to a first power supply;
- and
- a third transistor having a gate connected to said second global bitline, a source connected to a second power supply, and a drain connected to said local bitline, wherein said local bitline connects the memory cell to said sense amplifier.
Dependencies are inferred from the claim text.