# US 2008/0175080 A1 · Semiconductor memory device and test method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0175080 A1 - Document ID: US20080175080A1 - Status: Published application - Kind: A1 - Application number: 12/004,715 - Filed: 2007-12-21 - Published: 2008-07-24 - Earliest claimed: 2007-01-10 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Yong-Jun Kim; Woo-Seop Jeong; Kyu-Chan Lee - Web page: https://patentgrep.com/patent/US20080175080A1 ## CPC - G11C 29/56: External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor - G01R 31/318511: {Wafer Test} - G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]} - G11C 29/1201: {comprising I/O circuitry} - G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths - G11C 2029/5602: {Interface to device under test} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - G11C: STATIC STORES (semiconductor memory devices H10B) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits to the exterior. Therefore, it is possible to perform a test using plural channel pads during a wafer test of the semiconductor memory device using a plurality of probes of a probe card without incorrect contacts or non-contact with adjacent pads. ## Claims ### Claim 1 A semiconductor memory device comprising: a die in which a plurality of internal circuits are integrated; and a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits external to the semiconductor device. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the semiconductor device is configured to be wafer tested by a probe card having a pad pitch corresponding to one of the first channel pads and the second channel pads, and wherein the probe card can also test the semiconductor device using the other of the first channel pads and the second channel pads. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the semiconductor device is configured so that when a first wafer test is completed through one of the first channel pads and the second channel pads, a lateral movement corresponding to the pad pitch of the semiconductor device relative to the probe card enables a second wafer test to be performed through the other of the first channel pads and the second channel pads. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein the plurality of first and second channel pads have a pad size larger than the first pad size and a pad pitch larger than the first pad pitch, disposed in parallel in a straight line at a center part of the die, and divided into the plurality of multiple rows. ### Claim 5 (depends on 4) The semiconductor memory device according to claim 4, wherein the semiconductor device is configured so that when a first wafer test is completed through one of the first channel pads and the second channel pads, a vertical movement corresponding to the pad pitch of the semiconductor device relative to the probe card enables a second wafer test to be performed through the other of the first channel pads and the second channel pads. ### Claim 6 A semiconductor memory device comprising: a die in which a plurality of internal circuits are integrated; a plurality of pairs of first and second channel pads having a certain pad size and a certain pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows; a mode register for receiving an external mode setting code through predetermined pads of the plurality of pairs of first and second channel pads to output a mode setting signal for controlling a normal mode, or a first or second test mode; a switch control circuit for receiving the mode setting signal to output a switch control signal for connecting the plurality of pairs of first and second channel pads to a plurality of internal circuits, respectively, according to the normal mode or the first or second test mode; and a plurality of switching parts including a plurality of switches for connecting or disconnecting one of the plurality of pairs of first and second channel pads or the other of the plurality of first and second channel pads to or from the plurality of internal circuits, respectively, according to the switch control signal, wherein the plurality of pairs of first and second channel pads are configured to selectively contact test probes in an alternating manner during the first or second test mode to receive an external wafer test signal and output a signal generated by the plurality of internal circuits. ### Claim 7 (depends on 6) The semiconductor memory device according to claim 6, wherein the semiconductor device is configured to be wafer tested by a probe card having a pad pitch corresponding to one of the plurality of first channel pads and the plurality of second channel pads, and wherein the probe card can also test the semiconductor device using the other of the plurality of first channel pads and the plurality of second channel pads. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein the semiconductor device is configured so that when a first wafer test is completed through one of the plurality of pairs of first channel pads and the plurality of pairs of second channel pads, a lateral movement corresponding to the pad pitch of the semiconductor device relative to the probe card enables a second wafer test to be performed through the other of the plurality of pairs of first channel pads and the plurality of pairs of second channel pads. ### Claim 9 (depends on 6) The semiconductor memory device according to claim 6, wherein the mode register is connected to a plurality of address pads from among the plurality of pairs of first and second channel pads, the plurality of address pads configured to receive the mode setting code for entry and release of a first or second test mode, application of test items from the plurality of internal circuits, and test-related control signals, and to output the mode setting signal using a set of predetermined bits of the mode setting code. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein the mode register represents ON and OFF states of the plurality of switches from the plurality of switching parts according to the normal mode and the first and second test modes using a set of predetermined bits of the mode setting signal. ### Claim 11 (depends on 9) The semiconductor memory device according to claim 9, wherein the plurality of internal circuits comprise: a plurality of input buffers configured to receive a plurality of address signals, a plurality of data signals, and a plurality of control signals input through the plurality of pairs of first and second channel pads to output the signals after delaying the same for a predetermined time; a plurality of internal input circuits configured to receive the plurality of address signals, the plurality of data signals, and the plurality of control signals from the plurality of input buffers to perform independent operations, and to output internal operation signals required for performing an internal operation of the semiconductor memory device; a plurality of internal output circuits configured to receive the internal operation signals from the plurality of internal input circuits to perform independent operations, and to output output signals external to the semiconductor memory device; and a plurality of output buffers configured to receive the output signals output from the plurality of internal output circuits and to output the signals after delaying the same for a predetermined time. ### Claim 12 (depends on 6) The semiconductor memory device according to claim 6, wherein the plurality of switches comprises: a first switch configured to electrically connect or disconnect the plurality of first channel pads of the plurality of pairs of first and second channel pads to or from the plurality of input buffers or the plurality of output buffers; a second switch configured to electrically connect or disconnect the plurality of second channel pads of the plurality of pairs of first and second channel pads to or from the plurality of input buffers or the plurality of output buffers; and a third switch configured to electrically connect or disconnect the plurality of pairs of first and second channel pads to or from each other. ### Claim 13 (depends on 12) The semiconductor memory device according to claim 12, wherein the first and second switches are turned ON and the third switch is turned OFF during the normal mode, the first and third switches are turned ON and the second switch is turned OFF during the first test mode, and the second and third switches are turned ON and the first switch is turned OFF during the second test mode. ### Claim 14 A test method for a semiconductor memory device comprising: the semiconductor device comprising a die in which a plurality of internal circuits are integrated; and a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, the method comprising: receiving an external wafer test signal by selectively contacting the plurality of first and second channel pads with test probes in an alternating manner; and externally outputting a signal generated by the plurality of internal circuits to detect whether the semiconductor memory device is operating normally. ### Claim 15 (depends on 14) The test method according to claim 14, providing a probe card having a pad pitch corresponding to one of the plurality of first channel pads and the plurality of second channel pads, and testing semiconductor device using the probe card through the other of the plurality of first channel pads and the plurality of second channel pads. ### Claim 16 (depends on 15) The test method according to claim 15, wherein, when a first wafer test is completed through one of the plurality of first channel pads and the plurality of second channel pads, the method comprises performing a second wafer test through the other of the plurality of first channel pads and the plurality of second channel pads by laterally moving the wafer to be tested or the probe card by the pad pitch. ### Claim 17 (depends on 14) The test method according to claim 14, wherein the plurality of first and second channel pads have a pad size larger than the first pad size and a pad pitch larger than the first pad pitch, are parallely disposed in a straight line at a center part of the die, and are divided into the plurality of multiple rows. ### Claim 18 (depends on 17) The test method according to claim 17, wherein, when a first wafer test is completed through one of the plurality of first channel pads and the plurality of second channel pads, the method comprises performing a second wafer test through the other of the plurality of first channel pads and the plurality of second channel pads by vertically moving the wafer to be tested or the probe card by the pad pitch. ### Claim 19 A test method for a semiconductor memory device comprising: the semiconductor device comprising: a die in which a plurality of internal circuits are integrated; a plurality of pairs of first and second channel pads having a certain pad size and a certain pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows; a mode register for receiving an external mode setting code through predetermined pads of the plurality of pairs of first and second channel pads to output a mode setting signal for controlling a normal mode, or a first or second test mode; a switch control circuit for receiving the mode setting signal to output a switch control signal for connecting the plurality of pairs of first and second channel pads to a plurality of internal circuits, respectively, according to the normal mode or the first or second test mode; and a plurality of switching parts including a plurality of switches for connecting or disconnecting the plurality of pairs of first and second channel pads or the plurality of first and second channel pads to or from the plurality of internal circuits, respectively, according to the switch control signal, the test method comprising: selectively contacting the plurality of pairs of first and second channel pads with test probes in an alternating manner during the first or second test mode to receive an external wafer test signal; and outputting a signal generated by the plurality of internal circuits to detect whether the semiconductor memory device is operating normally. ### Claim 20 (depends on 19) The test method according to claim 19, further including providing a probe card having a pad pitch corresponding to one of the plurality of first channel pads and the plurality of second channel pads, and testing the semiconductor device using the probe card through the other of the plurality of first channel pads and the plurality of second channel pads. ### Claim 21 (depends on 20) The test method according to claim 20, wherein, when a first wafer test is completed through one of the plurality of first channel pads and the plurality of second channel pads, the method comprises performing a second wafer test through the other of the plurality of first channel pads and the plurality of second channel pads by laterally moving the wafer to be tested or the probe card by the pad pitch. ### Claim 22 (depends on 19) The test method according to claim 19, wherein the plurality of internal circuits comprises: a plurality of input buffers for receiving a plurality of address signals, a plurality of data signals, and a plurality of control signals input through the plurality of pairs of first and second channel pads to output the signals after delaying the same for a predetermined time; a plurality of internal input circuits for receiving the plurality of address signals, the plurality of data signals, and the plurality of control signals from the plurality of input buffers to perform independent operations, and outputting internal operation signals required for performing an internal operation of the semiconductor memory device; a plurality of internal output circuits for receiving the internal operation signals from the plurality of internal input circuits to perform independent operations, and outputting output signals external to the semiconductor memory device; and a plurality of output buffers for receiving the output signals output from the plurality of internal output circuits and outputting the signals after delaying the same for a predetermined time. ### Claim 23 (depends on 19) The test method according to claim 19, wherein the plurality of switches comprises: a first switch for electrically connecting or disconnecting the plurality of first channel pads of the plurality of pairs of first and second channel pads to or from the plurality of input buffers or the plurality of output buffers; a second switch for electrically connecting or disconnecting the plurality of second channel pads of the plurality of pairs of first and second channel pads to or from the plurality of input buffers or the plurality of output buffers; and a third switch for electrically connecting or disconnecting the plurality of pairs of first and second channel pads to or from each other. ### Claim 24 (depends on 23) The test method according to claim 23, wherein the first and second switches are turned ON and the third switch is turned OFF during the normal mode, the first and third switches are turned ON and the second switch is turned OFF during the first test mode, and the second and third switches are turned ON and the first switch is turned OFF during the second test mode.