Test scheme for fuse circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsSoon-Keun Jeon, Se-Hyun Hwang, Suk-Soo Pyo
Life of this patent
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Abstract
Provided is an apparatus and a method for testing an electrical fuse. In accordance therewith: a first test is performed on a plurality of memory cells arranged with a plurality of rows and a plurality of columns; a line related to a defective cell is repaired with a redundant line by using an electrical fuse; data outputted from the redundant line is set with a predetermined value; performing a second test on the plurality of memory cells; and a determination is made of whether or not data outputted from the line related to a defective cell has the predetermined value.
Claims15
A semiconductor memory device comprising:
- a plurality of main memory cells connected to a plurality of word lines and a plurality of bit lines;
- redundant memory cells connected to a plurality of redundant bit lines;
- an electrically-disconnectable electrical fuse circuit configured to repair a defective bit line connected to a defective main memory with the redundant line in response to an address signal, and to activate a redundant enable signal when the address signal designates the defective bit line during a test mode;
- and
- an input/output driver configured to change data outputted from the redundant memory cells into a predetermined value and to output the predetermined value as output data in response to the redundant enable signal during a test mode.
A semiconductor memory device comprising:
- a plurality of main memory cells connected to a plurality of word lines and a plurality of bit lines;
- redundant memory cells connected to a plurality of redundant bit lines;
- an electrically-disconnectable electrical fuse circuit configured to repair a defective word line connected to a defective main memory with the redundant line in response to an address signal, and to activate a redundant enable signal when the address signal designates the defective word line during a test mode;
- and
- an input/output driver configured to change data outputted from the redundant memory cells into a predetermined value and to output the predetermined value as output data in response to the redundant enable signal during the test mode.
A test system comprising:
- a semiconductor memory device;
- and
- a test device configured to provide an address signal, a data signal, control signals, and a test signal to the semiconductor memory device and to test the semiconductor memory device,
- wherein the semiconductor memory device includes:
- a plurality of main memory cells connected to a plurality of word lines and a plurality of bit lines;
- redundant memory cells connected to a plurality of redundant bit lines;
- and
- an electrically-disconnectable electrical fuse circuit configured to repair a defective bit line connected to a defective main memory with the redundant line in response to an address signal, and to activate a redundant enable signal when at least one bit line is repaired.
Dependencies are inferred from the claim text.