Semiconductor memory device

A semiconductor storage system comprising:

• a plurality of memory blocks which each comprise a single semiconductor memory device and a logic circuit which logically synthesizes outputs from the memory blocks,
• block selection signals being inputted to the individual operation control signal lines of the memory blocks as operation control signals,
• wherein the single semiconductor memory device comprises:
• a memory cell array which has a plurality of memory cells arranged in matrix form, a plurality of word lines connected to the memory cells, and a plurality of bit lines connected to the memory cells;
• a charge circuit which includes a plurality of charging transistors which charge the bit lines, respectively;
• a bit line reset circuit which includes a plurality of resetting transistors respectively forcing potentials of the bit lines to a ground potential,
• a read circuit which includes a plurality of reading transistors whose gates are each connected directly to the bit lines and which outputs information according to the on and off states of the reading transistors, and
• a bit line precharge circuit which includes a plurality of precharging transistors which charge the bit lines for a fixed time period,
• wherein the charge circuit includes a plurality of first operation controlling transistors which allow the charging transistors to effect charging operation, and
• the bit line precharge circuit includes a plurality of second operation controlling transistors which allow the precharging transistors to effect charging operation.