Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTomoharu TANAKA, Hiroshi NAKAMURA, Toru TANZAWA
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Abstract
A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.
Claims45
(canceled)
A semiconductor memory device comprising:
- a memory cell array having memory cells or memory cell units including at least one memory cell, the memory cells or the memory cell units being arranged in an array form;
- a bitline connected to at least one of the memory cells or the memory cell units;
- a
- read circuit including a precharge circuit;
- and
- a first transistor connected between the bitline and the read circuit,
- wherein a first voltage is applied to a gate of the first transistor during a first period, a second voltage is applied to the gate of the first transistor during a second period after the first period, a third voltage is applied to the gate of the first transistor during a third period after the second period, the bitline is precharged to a fourth voltage by the precharge circuit via the first transistor during the first period, the first voltage is higher than the third voltage, the second voltage is lower than the third voltage, and the read circuit senses a change in a voltage of the bitline during the third period or after the third period.
A semiconductor memory device comprising:
- a memory cell array having memory cell units including a plurality of memory cells connected in series, the memory cell units being arranged in an array form, the plurality of memory cells being located between a first select transistor and a second select transistor in the memory cell unit;
- a bitline connected to at least one of the memory cell units;
- a source line connected to the memory cell units;
- a read circuit including a precharge circuit;
- and
- a first transistor connected between the bitline and the read circuit,
- wherein the first select transistor and the second select transistor are respectively connected to the bitline and the source line, a first voltage is applied to a gate of the first transistor during a first period, a second voltage is applied to the gate of the first transistor during a second period after the first period, a third voltage is applied to the gate of the first transistor during a third period after the second period, the bitline is precharged to a fourth voltage by the precharge circuit via the first transistor during the first period, the first voltage is higher than the third voltage, the second voltage is lower than the third voltage, the read circuit senses a change in a voltage of the bitline during the third period or after the third period, the first period, the second period and the third period are included in a read operation or in a programming verify operation, and the first transistor is an n-channel MOS transistor.
Dependencies are inferred from the claim text.