Non-volatile semiconductor memory based on enhanced gate oxide breakdown

A method for programming a memory cell, said memory cell comprising a select transistor coupled in series with a data storage element, the data storage element comprising a gate, an ultra-thin dielectric underlying said conductive for physical storage of data, and a first doped region, said select transistor having a gate that is controllable to address said memory cell, said select transistor and data storage element formed in a P-well, the method comprising:

• said P-well biased at a voltage VBODY or left floating;
• applying a programming voltage Vpp to the conductive structure of the data storage element;
• and
• turning on said select transistor.

A programmable memory cell comprising:

• a pass transistor having a gate, a gate dielectric underlying the gate, and n-type first and second doped regions in a P-well, said n-type first and second doped regions in a spaced apart relationship to define a channel region therebetween under the gate;
• and
• a MOS data storage element having a gate, an ultra-thin dielectric underlying the gate, and a n-type first doped region in a P-well, said n-type first doped region being coupled to the n-type first doped region of the MOS field effect transistor, said MOS data storage element being programmed by breaking down said ultra-thin dielectric;
• wherein said P-well is formed on top of a body oxide, said body oxide formed atop of a substrate.

A method for programming a memory cell, said memory cell comprising a select transistor coupled in series with a data storage element, the data storage element comprising a gate, an ultra-thin dielectric underlying said gate, and a first doped region underlying both the ultra-thin dielectric and the conductive structure, said select transistor having a gate that is controllable to address said memory cell, said select transistor and data storage element formed in a P-well that is above a body oxide, said body oxide formed on top of a substrate, the method comprising:

• leaving said P-well floating and isolated by said body oxide;
• applying a programming voltage Vpp to the conductive structure of the data storage element;
• and
• turning on said select transistor.

A method for programming a memory cell, said memory cell comprising a select transistor coupled in series with a data storage element, the data storage element comprising a gate, an ultra-thin dielectric underlying said conductive for physical storage of data, and a first doped region underlying both the ultra-thin dielectric and the gate, said select transistor having a gate that is controllable to address said memory cell, said select transistor and data storage element formed in a P-well, said P-well formed in an N-well, the method comprising:

• leaving said P-well floating;
• applying a programming voltage Vpp to the conductive structure of the data storage element;
• and
• turning on said select transistor.