Flash Memory Device and Writing Method Thereof
AssigneeSamsung Electronics Co., Ltd.
InventorSeung-Won Lee
Life of this patent
Estimating the term…
Abstract
A flash memory device includes a memory cell array including a plurality of memory cells. A data writing buffer temporarily stores data to be written into the memory cells. A control circuit controls a write operation of the memory cells. A decoder decodes write address of the memory cell in response to the control circuit and regulating a constant current to flow through a selected bit line with reference to a result of the decoding. The decoder decodes an address and controls a current in units of a memory cell during a normal writing mode and decodes an address and controls a current in units of a memory block during a test writing mode.
Claims20
A flash memory device comprising:
- a memory cell array comprising a plurality of memory cells;
- a data writing buffer temporarily storing data to be written into the memory cells;
- a control circuit configured to control a write operation of the memory cells;
- and
- a decoder configured to decode a write address of the memory cell in response to the control circuit and regulating a constant current to flow through a selected bit line with reference to a result of the decoding,
- wherein the decoder decodes an address and controls a current in units of a memory cell during a normal write mode, and decodes an address and controls a current in units of a memory block during a test writing mode.
A flash memory device comprising:
- a memory cell array comprising a plurality of memory cells;
- a data writing buffer temporarily storing data to be written into the memory cells;
- a control circuit configured to control a write operation of the memory cells;
- and
- a decoder configured to decode a write address of the memory cell in response to the control circuit and regulating a constant current to flow through a selected bit line with reference to a result of the decoding,
- wherein the decoder comprises:
- a decoding circuit decoding an address in units of a memory cell during a normal writing mode, and decoding an address in units of a memory block during a test writing mode;
- a current regulator controlling a constant writing current to flow into a selected bit line in response to a result of the decoding and a bias voltage;
- and
- a bias circuit providing the bias voltage to the current regulator.
A method of writing data into a flash memory, comprising:
- determining an operation mode of the flash memory;
- decoding an address in a unit of a memory cell when the operation mode is determined to be in a normal writing mode;
- regulating a constant current to flow through a bit line of the decoded memory cell;
- writing the decoded memory cell with data stored in a write buffer through the bit line;
- decoding an address in a unit of a memory block when the operation mode is determined to be in a test writing mode;
- regulating a constant current to flow through a bit line of the decoded memory block;
- and
- writing the decoded memory block with data stored in the write buffer through the bit line.
Dependencies are inferred from the claim text.