Non-volatile memory array

A method of operating the non-volatile memory for a non-volatile memory array comprising a plurality of memory units, and each memory unit comprises an N type well region disposed in the substrate;

• a P type drain region, a P type doped region and a P type source region disposed in the N type well region;
• a select gate disposed on the substrate between the P type source region and the P type doped region;
• a control gate disposed on the substrate between the P type doped region and the P type drain region;
• and a charge storage layer disposed between the control gate and the substrate, wherein the two neighboring units on the same row are disposed a mirror symmetry manner;
• a plurality of drain lines arranged in parallel in column direction to connect with the P type drain region of each memory unit in one column;
• a plurality of bit lines arranged in parallel in row direction and connected with the P type source region of each memory unit in one row;
• a plurality of word lines arranged in parallel in column direction and connected with the select gate of each memory unit in one column;
• and a plurality of control lines arranged in parallel in column direction and connected with the control gate of each memory unit in one column, wherein every two control lines are electrically connected together and the two columns of memory units with the electrically connected control lines compose one page as well as the two neighboring memory units in one page in the row direction commonly share the P type drain region;
• the method comprises:
• applying a first voltage to all of the word lines, applying a second voltage to all of the control lines, floating all of the bit lines, applying a third voltage to all of the drain lines, and applying a fourth voltage to the N type well region so that the non-volatile memory array is in a standby state.