Memory cell programming method and semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorDong-ku KANG
Life of this patent
Estimating the term…
Abstract
A memory cell programming method and related semiconductor memory device are disclosed. The method involves receiving and latching first through nth bits of write data in a corresponding plurality of first through nth latches, and programming a kth bit of write data in the memory cell, where k ranges from 2 to n, in relation to first through k-1th bits of write data previously stored in the memory cell.
Claims17
A method of programming multi-bit data in a memory cell, comprising:
- respectively receiving and latching first through nth bits of write data in a corresponding plurality of first through nth latches;
- and
- programming a kth bit of write data in the memory cell, where k ranges from 2 to n, in relation to first through k-1 th bits previously latched in first through k-1 th latches.
A method of programming multi-bit data in a memory cell, the memory cell being arranged in a memory cell array of a semiconductor memory device comprising a sequentially related plurality of first through nth latches, the method comprising:
- receiving and latching a kth bit of write data in the first latch, where k is a natural number ranging from 1 to n and programming the kth bit of data in the memory cell from the first latch;
- transferring the kth bit of write data to a second latch in the plurality of latches, and receiving and latching a kth+1 bit of write data in the first latch;
- and
- programming the kth+1 bit of write data in the memory cell from the first latch in relation to the kth bit of write data latched in the second latch.
A semiconductor memory device comprising:
- a multi-level memory cell configured to store first through nth bits of write data;
- and
- a plurality of first through nth latches, each one of the plurality of first through nth latches being configured to receive and latch a corresponding one of the first through nth bits of write data,
- wherein the plurality of first through nth latches are further configured to sequentially program a kth bit of write data, where k is a natural number ranging from 2 to n, in the memory cell in relation to first through k-1th bits of write data previously latched in first through k-1th latches.
Dependencies are inferred from the claim text.