Depletion-mode mosfet circuit and applications
AssigneeKeystone Semiconductor Corp.
InventorWEN T. LIN
Life of this patent
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Abstract
Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.
Claims16
A static, random access memory device, comprising:
- a memory, buffer cell comprising at least one depletion MOSFET transistor.
A four-transistor boolean logic circuit comprising at least two depletion MOSFET transistors.
An electrostatic discharge protection circuit, comprising:
- an N type depletion MOSFET transistor;
- a P type depletion MOSFET transistor;
- a ground terminal coupled to a source terminal of said P type depletion MOSFET transistor and to both a gate terminal and a substrate terminal of said N type depletion MOSFET transistor;
- a positive power terminal coupled to a source terminal of said N type depletion MOSFET transistor and to both a gate terminal and a substrate terminal of said P type depletion MOSFET transistor;
- an input terminal coupled to a drain terminal of both said N type depletion MOSFET transistor and said P type depletion MOSFET transistor;
- and
- an output terminal coupled to said input terminal, thereby providing electrostatic discharge protection circuit.
Dependencies are inferred from the claim text.