Memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods

A resistive semiconductor memory device having a three-dimensional stack structure, the resistive semiconductor memory device comprising:

• a plurality of bit line layers comprising a plurality of main bit line layers and a plurality of sub bit line layers alternately stacked, wherein each of the plurality of main bit line layers comprises a plurality of main bit lines and each of the plurality of sub bit line layers comprises a plurality of sub bit lines;
• a plurality of memory cell layers each disposed between corresponding main and sub bit line layers and comprising a plurality of memory cells each comprising a main unit cell and a sub unit cell;
• and,
• a plurality of word line layers disposed in the plurality of memory cell layers, respectively, and each comprising a plurality of word lines each shared by main unit cells and sub unit cells of a predetermined of corresponding memory cells.

A resistive semiconductor memory device having a three-dimensional stack structure, the resistive semiconductor memory device comprising:

• a plurality of array block layers each comprising a main bit line layer, a memory cell layer comprising a main unit cell layer, a sub unit cell layer, and a word line layer interposed therebetween and shared thereby, and a sub bit line layer sequentially stacked,
• wherein:
• in each of the plurality of array block layers,
• the main bit line layer comprises a plurality of main bit lines,
• the sub bit line layer comprises a plurality of sub bit lines,
• the main unit cell layer comprises a plurality of main unit cells,
• the sub unit cell layer comprises a plurality of sub unit cells, and
• each of pairs of main and sub unit cells neighboring each other along a vertical direction in each memory cell layer form a memory cell.

A method for performing a read operation in a semiconductor memory device having a three-dimensional stack structure and comprising a plurality of main bit lines, a plurality of sub bit lines, a plurality of word lines, and a plurality of memory cells each comprising a main unit cell and a sub unit cell sharing one word line, the method comprising:

• selecting a main bit line, a sub bit line, and a word bit line connected to a memory cell to select the memory cell;
• applying a read bias voltage to the selected main bit line and the selected sub bit line and a ground voltage to the selected word line, and simultaneously, applying the ground voltage to unselected main bit lines and unselected sub bit lines and the read bias voltage to unselected word lines;
• and,
• comparing a voltage level apparent on the selected main bit line to a voltage level apparent on the selected sub bit line and determining whether the selected memory cell is storing a first data value having a first logic level or a second data value having a second logic level.