Video Control for Providing Multiple Screen Resolutions Using Modified Timing Signal
AssigneePalm, Inc.
InventorMostafa Kashi
Life of this patent
Estimating the term…
Abstract
A video controller providing control signals for one or more screen resolutions. The video controller does not change or modify the pixel data for a video signal with a screen resolution. Accordingly, the video controller does not require additional computing or memory resources. Furthermore, because the video controller can be implemented by counters and logic gates, the video controller does not require additional hardware resources. The video controller also provides a convenient architecture for scrolling images with a higher screen resolution in a viewing device that only supports a lower screen resolution.
Claims23
A method of controlling a viewing device comprising:
- receiving a first timing signal and a second timing signal at a video controller, the first timing signal and the second timing signal associating pixel data with a plurality of pixels of a first image in a first screen resolution;
- generating a third timing signal from the first timing signal and the second timing signal, the third timing signal in conjunction with the second timing signal associating the pixel data with a plurality of pixels of a second image in a second screen resolution;
- and
- transmitting the second timing signal and the third timing signal to a viewing device operable to display the second image in the second screen resolution to display the second image on the viewing device.
A delay module for use in a video control device, the delay module comprising:
- a receiving module configured to receive a first timing signal and a second timing signal, the first timing signal and the second timing signal associating pixel data with a plurality of first pixels of a first image in a first screen resolution;
- and
- a gate module coupled to the receiving module, the gate module configured to generate a third timing signal from the first timing signal and the second timing signal, the third timing signal in conjunction with the second timing signal associating the pixel data with a plurality of second pixels of a second image in a second screen resolution.
A computing device comprising:
- a processor;
- a data storage device coupled to the processor;
- and
- a display controller, coupled to the processor, the display controller comprising:
- a receiving module configured to receive a first timing signal and a second timing signal, the first timing signal and the second timing signal associating pixel data with a plurality of first pixels of a first image in a first screen resolution;
- and
- a gate module coupled to the receiving module, the gate module configured to generate a third timing signal from the first timing signal and the second timing signal, the third timing signal in conjunction with the second timing signal associating the pixel data with a plurality of second pixels of a second image in a second screen resolution.
Dependencies are inferred from the claim text.