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US 2008/0174580 A1Published application
Gate Driver and Driving Method Thereof in Liquid Crystal Display
AssigneeAu Optronics Corporation
InventorsLee-Hsun Chang, Chung-Lung Li, Yu-Wen Lin, Yung-Tse Cheng
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Abstract
A gate driver includes several first and second circuit units outputting first and second driving signals to odd and even gate lines, respectively, and each of the first circuit units or the second circuit units includes a signal output unit for outputting the driving signal and a shift register unit for outputting a start signal to a next circuit unit. A driving method is also disclosed.
Claims22
A gate driver for driving a plurality of gate lines in a liquid crystal display, the gate driver comprising:
- a first circuit unit for outputting a first driving signal to one odd gate line of the gate lines, comprising:
- a first signal output unit for receiving a first odd start signal and a first input signal to generate the first driving signal;
- and
- a first shift register unit for receiving the first odd start signal and a first clock signal to generate a second odd start signal;
- a second circuit unit for outputting a second driving signal to another odd gate line of the gate lines, the second circuit unit electrically coupling to the first circuit unit and comprising:
- a second signal output unit for receiving the second odd start signal and the first input signal to generate the second driving signal;
- and
- a second shift register unit for receiving the second odd start signal and the first clock signal to generate a third odd start signal;
- a third circuit unit for outputting a third driving signal to one even gate line of the gate lines, comprising:
- a third signal output unit for receiving a first even start signal and a second input signal to generate the third driving signal;
- and
- a third shift register unit for receiving the first even start signal and a second clock signal to generate a second even start signal;
- and
- a fourth circuit unit for outputting a fourth driving signal to another even gate line of the gate lines, the fourth circuit unit electrically coupling to the third circuit unit and comprising:
- a fourth signal output unit for receiving the second even start signal and the second input signal to generate the fourth driving signal;
- and
- a fourth shift register unit for receiving the second even start signal and the second clock signal to generate a third even start signal.
14 more elements
A liquid crystal display, comprising:
- a plurality of data lines;
- a plurality of gate lines crossing the data lines to form a display cell array;
- a data driver coupled to the data lines and generating a plurality of image signals to the data lines;
- and
- a gate driver coupled to the gate lines and generating a plurality of driving signals to the gate lines, the gate driver comprising:
- a plurality of first circuit units, which are electrically cascade-connected, coupled to odd gate lines of the gate lines and outputting a plurality of first driving signals to the odd gate lines, wherein each of the first circuit units comprises a first signal output unit and a first shift register unit, and the first signal output unit receives a first input signal and a first start signal to generate the first driving signal, and the first shift register unit receives the first start signal and a first clock signal to generate a next first start signal for a next first circuit unit of the first circuit units and transmits the next first start signal to the next first circuit unit;
- and
- a plurality of second circuit units, which are electrically cascade-connected, coupled to even gate lines of the gate lines and outputting a plurality of second driving signals to the even gate lines, wherein each of the second circuit units comprises a second signal output unit and a second shift register unit, and the second signal output unit receives a second input signal and a second start signal to generate the second driving signal, and the second shift register unit receives the second start signal and a second clock signal to generate a next second start signal for a next second circuit unit of the second circuit units and transmits the next second start signal to the next second circuit unit.
5 more elements
Dependencies are inferred from the claim text.