Differential impedance matching circuit and method with harmonic suppression
AssigneeIntegration Associates Inc.
InventorsAttila Zolomy, Peter Onody, Tibor Toro
Life of this patent
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Abstract
Matching network circuits and a method are shown for suppressing a harmonic frequency in a matching network. The circuits and method involve impedance matching first and second differential input nodes to a single ended output node using a first reactive impedance selected to pass a resonant frequency. They also involve suppressing a harmonic frequency of a common mode signal presented at the first and second differential input nodes by providing a series resonance from the first and second differential input nodes to a radio frequency ground potential, where the series resonance is selected to pass the harmonic frequency to the radio frequency ground potential.
Claims5
A matching network, the network comprising:
- first and second differential input nodes and a single ended output node;
- a first inductor coupled between the first differential input node and a common circuit node;
- a second inductor coupled between the second differential input node and the common circuit node;
- a third inductor coupled between a first power supply rail and the common circuit node;
- a first capacitor coupled between the first differential input node and the single ended output node;
- a second capacitor coupled between the second differential input node and a radio frequency ground node;
- a fourth inductor coupled between the second differential input node and the single ended output node;
- a third capacitor coupled between the common circuit node and the radio frequency ground node, where a capacitance of the third capacitor is selected to provide second harmonic suppression of a common mode signal present at the first and second differential input nodes.
An inductive matching network, the network comprising:
- first and second differential input nodes and a single ended output node;
- a first inductor coupled between the first differential input node and a first power supply rail;
- a second inductor coupled between the second differential input node and the single ended output node;
- a third inductor coupled between a radio frequency ground node and a common circuit node, where an inductance of the third inductor is selected to provide second harmonic suppression of a common mode signal present at the first and second differential input nodes;
- a fourth inductor coupled between the second differential input node and the first power supply rail;
- a first capacitor coupled between the first differential input node and the common circuit node;
- a second capacitor coupled between the second differential input node and the common circuit node;
- and
- a third capacitor coupled between the first differential input node and the single ended output node.
A method for suppressing a harmonic frequency in a matching network, the method comprising the steps of:
- impedance matching first and second differential input nodes to a single ended output node using a first reactive impedance selected to pass a resonant frequency;
- and
- suppressing a harmonic frequency of a common mode signal presented at the first and second differential input nodes by providing a series resonance from the first and second differential input nodes to a radio frequency ground potential, where the series resonance is selected to pass the harmonic frequency to the radio frequency ground potential.
Dependencies are inferred from the claim text.