# US 2008/0174363 A1 · Output stage for electronic devices integrated on a semiconductor substrate, in particular for high frequency applications and corresponding method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0174363 A1 - Document ID: US20080174363A1 - Status: Published application - Kind: A1 - Application number: 11/972,234 - Filed: 2008-01-10 - Published: 2008-07-24 - Earliest claimed: 2007-01-24 - Assignees: STMicroelectronics S.r.l.; Politecnico Di Milano - Inventors: Paolo PULICI; Michele Bartolini; Pier Paolo Stoppino - Web page: https://patentgrep.com/patent/US20080174363A1 ## CPC - H03K 19/00384: {in field effect transistor circuits} - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An output stage may include an input terminal receiving an input signal, an output terminal coupled to an external load, and a pre-buffer coupled to the input terminal and including an enable terminal receiving a general enable signal and a first output terminal for supplying a first control signal. The output stage may also include an output buffer including a first final transistor inserted between the supply terminal and the output terminal, and a control terminal coupled to the first output terminal of the pre-buffer for receiving the first control signal, and a first tracking circuit between the supply terminal and the first output terminal of the pre-buffer. The first tracking circuit may include a first capacitor between the supply terminal and a first intermediate node coupled to the first output terminal of the pre-buffer by a switch activated by a first activation signal during a transient of the first final transistor thereby reconstructing a noise of the first reference voltage. ## Claims ### Claim at position 1 1-15. (canceled) ### Claim 16 An output stage for an electronic circuit between a supply terminal receiving a first reference voltage and a reference terminal being maintained at a second reference voltage, the output stage comprising: at least one input terminal to receive an input signal; an output terminal to be coupled to an external load; a pre-buffer coupled to said at least one input terminal and comprising an enable terminal to receive a general enable signal and at least one first output terminal for supplying a first control signal; an output buffer comprising at least one first transistor between the supply terminal and said output terminal, and a control terminal coupled to said at least one first output terminal of said pre-buffer for receiving the first control signal; and at least one first tracking circuit between the supply terminal and said at least one first output terminal of said pre-buffer, said at least one first tracking circuit comprising a first intermediate node, a switch activated by a first activation signal during at least one transient of said at least one first transistor, and a first capacitor between the supply terminal and said first intermediate node, said first intermediate node to be coupled to said at least one first output terminal of said pre-buffer by way of said switch, thereby reconstructing a noise of the first reference voltage. ### Claim 17 (depends on 16) The output stage according to claim 16 wherein said pre-buffer comprises a first inverter, and at least one second inverter coupled in series to each other between said at least one input terminal and said at least one first output terminal of said pre-buffer; wherein said at least one second inverter comprises a first transistor, and a second transistor, said first transistor being coupled in series to said second transistor and being between the supply terminal and the reference terminal; and further comprising a first enable circuit between said second transistor and the reference terminal for bringing said at least one first output terminal of said pre-buffer to a tri-state condition. ### Claim 18 (depends on 17) The output stage according to claim 17 further comprising a first logic circuit having an output terminal and at least one first input; wherein said first enable circuit comprises a first enable terminal coupled to said output terminal of said first logic circuit; wherein said first logic circuit receives a first enable signal and said at least one first input receives the first control signal enabled by a first inner enable signal, delayed with respect to the general enable signal, received at a common input terminal and for generating on said at least one first output terminal of said pre-buffer the first enable signal being equal to the first control signal. ### Claim 19 (depends on 18) The output stage according to claim 18 further comprising a first delay circuit having an output terminal and being coupled between said enable terminal of said pre-buffer and said output terminal of said first delay circuit; and wherein said first delay circuit is for supplying said output terminal of said first delay circuit with the first inner enable signal, and also for supplying an intermediate output terminal with a second inner enable signal, the first inner enable signal being based upon a NOT function of the second inner enable signal, the general enable signal being equal to the first inner enable signal. ### Claim 20 (depends on 19) The output stage according to claim 19 further comprising a first activation circuit, and a second logic circuit having an output terminal and at least one first input; wherein said first enable circuit further comprises a second enable terminal coupled to said output terminal of said second logic circuit; and wherein said at least one first input of said second logic circuit receives a first activation delayed signal generated by said first activation circuit and enabled by the first inner enable signal received at a common input terminal and for generating on said at least one first output terminal of said second logic circuit a second enable signal being equal to the first activation delayed signal. ### Claim 21 (depends on 20) The output stage according to claim 20 wherein said first activation circuit comprises an input terminal coupled to said at least one first output terminal of said pre-buffer, an output terminal for supplying the first activation delayed signal, and an intermediate terminal for supplying the first activation signal corresponding to a signal opposed to the first control signal of said pre-buffer; and wherein the first activation delayed signal is a signal opposed to the first control signal and has a delayed switch in time with respect to the first control signal. ### Claim 22 (depends on 21) The output stage according to claim 21 further comprising a second delay circuit comprising an output terminal; and wherein said at least one first tracking circuit further comprises a second transistor comprising a first conduction terminal coupled to the reference terminal, a second conduction terminal coupled to the first intermediate node, and a control terminal coupled to said output terminal of said second delay circuit, said second delay circuit being driven by an input delayed signal. ### Claim 23 (depends on 16) The output stage a according to claim 16 wherein said pre-buffer includes a second output terminal for supplying a second control signal; wherein said output buffer comprises at least one second transistor between the reference terminal and said second output terminal and having a control terminal coupled to said output terminal of said pre-buffer and receiving therefrom the second control signal; and further comprising at least one second tracking circuit between the reference terminal and said second output terminal of said pre-buffer, and a second capacitor between the reference terminal and a second intermediate node being coupled to said second output terminal of said pre-buffer by a switch activated by a second activation signal during at least one transient of said at least one second transistor. ### Claim 24 An electronic device comprising: a supply terminal receiving a first reference voltage; a reference terminal being maintained at a second reference voltage; and an output stage between said supply terminal and said reference terminal and comprising at least one input terminal to receive an input signal, an output terminal to be coupled to an external load, a pre-buffer coupled to said at least one input terminal and comprising an enable terminal to receive a general enable signal and at least one first output terminal for supplying a first control signal, an output buffer comprising at least one first transistor between the supply terminal and said output terminal, and a control terminal coupled to said at least one first output terminal of said pre-buffer for receiving the first control signal, and at least one first tracking circuit between the supply terminal and said at least one first output terminal of said pre-buffer, said at least one first tracking circuit comprising a first intermediate node, a switch activated by a first activation signal during at least one transient of said at least one first transistor, and a first capacitor between the supply terminal and said first intermediate node, said first intermediate node to be coupled to said at least one first output terminal of said pre-buffer by way of said switch, thereby reconstructing a noise of the first reference voltage. ### Claim 25 (depends on 24) The electronic device according to claim 24 wherein said pre-buffer comprises a first inverter, and at least one second inverter coupled in series to each other; wherein said at least one second inverter comprises a first transistor, and a second transistor, said first transistor being coupled in series to said second transistor and being between the supply terminal and the reference terminal, and wherein said output stage further comprises a first enable circuit between said second transistor and the reference terminal, said first enable circuit for bringing said at least one first output terminal of said pre-buffer to a tri-state condition. ### Claim 26 (depends on 24) The electronic device a according to claim 24 wherein said pre-buffer includes a second output terminal for supplying a second control signal; wherein said output buffer comprises at least one second transistor between the reference terminal and said second output terminal and having a control terminal coupled to said output terminal of said pre-buffer and receiving therefrom the second control signal; and wherein said output stage further comprises at least one second tracking circuit between the reference terminal and said second output terminal of said pre-buffer, and a second capacitor between the reference terminal and a second intermediate node being coupled to said second output terminal of said pre-buffer by a switch activated by a second activation signal during at least one transient of said at least one second transistor. ### Claim 27 A method for driving an output stage for an electronic circuit between a supply terminal receiving a first reference voltage and a reference terminal being maintained at a second reference voltage, the output stage comprising at least one input terminal to receive an input signal, an output terminal to be coupled to an external load, a pre-buffer to be coupled to the at least one input terminal and comprising an enable terminal receiving a general enable signal and at least one first output terminal for supplying a first control signal, an output buffer comprising at least one first transistor between the supply terminal and the output terminal, and having a control terminal coupled to the at least one first output terminal of the pre-buffer for receiving the first control signal, and at least one first tracking circuit between the supply terminal and the at least one first output terminal of the pre-buffer, the at least one first tracking circuit having a first capacitor between the supply terminal and a first intermediate node, the first intermediate node to be coupled to the at least one first output terminal of the pre-buffer by a switch activated by a first activation signal, the method comprising: activating the at least one first transistor of the output buffer to generate the corresponding first control signal on the at least one first output terminal of the pre-buffer; and replicating, at least in a transient, the first reference voltage from the supply terminal on the control terminal of the at least one first transistor by at least reconstructing a noise present in the first reference voltage. ### Claim 28 (depends on 27) The method according to claim 27 wherein the reconstructing further comprises: bringing the at least one first output terminal of the pre-buffer to a tri-state condition; coupling a first capacitor of the at least one first tracking circuit to the at least one first output terminal of the pre-buffer; and generating the first activation signal by at least one first switch. ### Claim 29 (depends on 28) The method according to claim 28 further comprising disconnecting the at least one first tracking circuit from the at least one first output terminal of the pre-buffer, the disconnecting comprising switching off of the at least one first switch by switching of the first activation signal and an activation of a second transistor of the at least one first tracking circuit by a first input delayed signal supplied by a second delayed circuit. ### Claim 30 (depends on 29) The method according to claim 29 further comprising activating a first activation circuit of the pre-buffer by at least switching of a second enable signal, and generating the first control signal on the basis of the input signal. ### Claim 31 (depends on 30) The method according to claim 30 wherein the bringing comprises generating a first enable signal at an enable terminal of a first enable circuit, the first enable signal being supplied by a first logic circuit and corresponding to the first control signal. ### Claim 32 (depends on 31) The method according to claim 31 wherein the generating of the first enable signal comprises generating the second enable signal at a second enable terminal of the first enable circuit, the second enable signal being supplied by a second logic circuit and corresponding to a first activation delayed signal at the output of the first activation circuit. ### Claim 33 (depends on 27) The method according to claim 27 wherein the output buffer comprises at least one second transistor; and further comprising switching off of the at least one second transistor before the activating.