US 2008/0174359 A1 · SEMICONDUCTOR INTEGRATED CIRCUIT

Abstract

A substrate bias technique is used in an active mode enabling a high yield, and an operating consumption power and the fluctuation of a signal delay in signal processing are reduced in the active mode. The additional PMOS and NMOS of the additional capacitance circuit are produced in the same production process as the PMOSs and the NMOSs of the CMOS circuits. The gate capacitance of the additional PMOS is coupled between the power supply wiring and the N well and the gate capacitance of the additional NMOS is coupled between the ground wiring and the P well. The noise on the power supply wiring is transmitted to the N well through the gate capacitance and the noise on the ground wiring is transmitted to the P well through the gate capacitance. The fluctuation of noise on the substrate bias voltage between the source and the well of PMOS and NMOS of the CMOS circuits is reduced.

Claims20

Dependent claims

A semiconductor integrated circuit comprising:

a CMOS circuit processing an input signal;
and
an additional capacitance circuit produced in the same production process as the CMOS circuit,
wherein the CMOS circuit and the additional capacitance circuit include PMOSs and an additional PMOS with an N well and NMOSs and an additional NMOS with a P well,
wherein the sources of the PMOSs in the CMOS circuit and the additional PMOS in the additional capacitance circuit are electrically coupled to a first operating voltage wiring and the sources of the NMOSs in the CMOS circuit and the additional NMOS in the additional capacitance circuit are electrically coupled to a second operating voltage wiring,
wherein the N well can be supplied with a PMOS substrate bias voltage and the P well can be supplied with an NMOS substrate bias voltage, and
wherein the gate electrode of the additional PMOS in the additional capacitance circuit is electrically coupled to the N well and the gate electrode of the additional NMOS in the additional capacitance circuit is electrically coupled to the P well.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit

Life of this patent

Semiconductor integrated circuit

Life of this patent

Abstract

Claims20