Wide-locking range phase locked loop circuit using adaptive post division technique
AssigneeFaraday Technology Corp.
InventorsRen-Hong Luo, Cheng-Ta Wei
Life of this patent
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Abstract
A wide-locking range phase locked loop circuit includes a decision unit and a closed loop connection comprising a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a multi-modulus divider. The decision unit receives a phase difference signal outputted from phase frequency detector and the control voltage outputted from the loop filter and determines to select a specific divisor form the plurality of divisors provided by the multi-modulus divider if the phase difference signal indicates an unlocked state and the control voltage is not within a standard voltage operation range.
Claims13
A phase locked loop circuit including:
- a phase frequency detector receiving a frequency divided signal and an input clock signal with a reference frequency and detecting the difference in phase and frequency between the input clock signal and the frequency divided signal and then outputting a phase difference signal;
- a charge pump outputting an output current in response to the phase difference signal;
- a loop filter generating a control voltage in response to the phase difference signal;
- a voltage controlled oscillator generating a voltage controlled clock signal with a voltage controlled frequency in response to the control voltage;
- a multi-modulus divider receiving the voltage controlled clock signal and then generating the frequency divided signal and an output clock signal with an output frequency, wherein a first divisor can be selected from a plurality of divisors provided by the multi-modulus divider to achieve a relation that the voltage controlled frequency divided by the first divisor equals the output frequency;
- and
- a decision unit receiving the phase difference signal and the control voltage and determining to select a second divisor form the plurality of divisors provided by the multi-modulus divider if the phase difference signal indicates an unlocked state and the control voltage is not within a standard voltage operation range.
A method of controlling a phase locked loop circuit, wherein the phase locked loop circuit divides a voltage controlled clock signal by a divisor for generating a frequency divided signal and generates a control voltage in response to a difference between the frequency divided signal and an input clock signal, the method including steps of:
- setting the divisor to an initial value;
- and
- changing the divisor if the control voltage is not within a standard voltage operation range over a period of time.
Dependencies are inferred from the claim text.