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US 2008/0174347 A1Published application
Clock synchronization system and semiconductor integrated circuit
AssigneeNEC Electronics Corporation
InventorYoshinobu OSHIMA
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Abstract
A clock synchronization system includes a phase-locked loop to generate a multiplied clock based on a reference clock, a frequency divider to generate a plurality of frequency-divided clocks based on the multiplied clock, and a frame pulse generator to generate a frame pulse by frequency-dividing the reference clock, wherein the frequency-divided clocks are phase-locked by the frame pulse.
Claims16
A clock synchronization system comprising:
- a phase synchronization circuit to generate a multiplied clock based on a reference clock;
- a frequency divider to generate a plurality of frequency-divided clocks based on the multiplied clock;
- and
- a frame pulse generator to generate a frame pulse by frequency-dividing the reference clock, wherein
- the frequency-divided clocks are phase-locked by the frame pulse.
2 more elements
A clock synchronization system comprising:
- a first phase synchronization circuit to generate a first multiplied clock based on a reference clock;
- a second phase synchronization circuit to generate a second multiplied clock based on the reference clock;
- a first frequency divider to generate a first frequency-divided clock based on the first multiplied clock;
- a second frequency divider to generate a second frequency-divided clock based on the second multiplied clock;
- and
- a frame pulse generator to generate a frame pulse by frequency-dividing the reference clock, wherein
- the first frequency-divided clock and the second frequency-divided clock are phase-locked by the frame pulse.
4 more elements
Dependencies are inferred from the claim text.