Method and apparatus for measuring the duty cycle of a digital signal
AssigneeIBM Corporation
InventorsDavid William Boerstler, Eskinder Hailu, Jieming Qi
Life of this patent
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Abstract
The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.
Claims10
A method of determining duty cycle information for a variable duty cycle circuit, the method comprising:
- providing, by a clock signal generator, a clock signal to the variable duty cycle circuit, the variable duty cycle circuit in response providing an output signal which exhibits a duty cycle dependent on a duty cycle index, the output signal exhibiting a first frequency;
- providing, by the variable duty cycle circuit, the output signal to a divider circuit which fails at a maximum frequency dependent on the duty cycle index;
- and
- sweeping, by the clock signal generator, the frequency of the clock signal from the first frequency up to a second frequency above which divider circuit failure occurs;
- and
- determining duty cycle information for the output signal from the second frequency.
A method of determining duty cycle information for a duty cycle correction (DCC) circuit, the method comprising:
- providing, by a clock signal generator, a first clock signal exhibiting a duty cycle to the DCC circuit;
- receiving, by the DCC circuit, a plurality of duty cycle indexes;
- generating, by the DCC circuit, a second clock signal for each duty cycle index, the duty cycle of each second clock signal relating to each duty cycle index, respectively;
- receiving, by a divider circuit, the second clock signal, the divider circuit failing at a different maximum frequency for each duty cycle index;
- sweeping for each duty cycle index, by the clock signal generator, the frequency of the first clock signal from a first frequency up to second maximum frequency above which divider circuit failure occurs, thus providing a second maximum frequency value corresponding to each duty cycle index, respectively;
- and
- determining, from the second maximum frequency value corresponding to each duty cycle index, duty cycle information corresponding to each respective duty cycle index.
Dependencies are inferred from the claim text.