Comparator with complementary differential input stages
AssigneePotentia Semiconductor, Inc.
InventorRoger Colbeck
Life of this patent
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Abstract
A comparator comprises complementary (e.g. NMOS and PMOS) comparator cells having overlapping common mode input voltage ranges which together extend approximately from rail to rail. A digital logic arrangement, including edge detectors, gates, and a latch, is responsive to transitions at the outputs of the comparator cells to set the latch in response to the earliest rising edge and to reset the latch in response to the earliest falling edge. An output of the latch constitutes an output of the comparator. Consequently the comparator is edge-sensitive with a speed optimized for a wide common mode input voltage range. Additional logic gates can provide level-sensitive control of the latch.
Claims7
A comparator comprising:
- a first comparator cell responsive to a first range of input voltages for providing a first comparison signal;
- a second comparator cell responsive to a second range of input voltages, overlapping the first range, for providing a second comparison signal;
- and
- a logic arrangement responsive to the first and second comparison signals to provide a comparator output signal, the logic arrangement being responsive to a transition of the first comparison signal or a transition of the second comparison signal, whichever occurs first, representing a first change of comparison result to provide a first state of the comparator output signal, and being responsive to a transition of the first comparison signal or a transition of the second comparison signal, whichever occurs first, representing a second change of comparison result opposite to the first change to provide a second state of the comparator output signal opposite to said first state.
Dependencies are inferred from the claim text.