Filter circuit for removing noise pulses from digital input signal

A filter circuit comprising:

• an input-signal processing section configured to:
• output a sample of a digital input signal at a first sampled level, the digital input signal sampled according to a clock signal, the sample output at the first sampled level when a level of the digital input signal is constant between sampling points, and
• output the sample at a reversed sample level when the level of the digital input signal changes between the sampling points;
• and
• a signal-level determining section that outputs a sample signal at a first level when all of one or more delayed versions of the sample are at the first level, and outputs a signal at a second level when all of the one or more delayed versions of the sample are at the second level.

A signal processing circuit for implementing a digital filter, the signal processing circuit comprising:

• a digital sample-and-hold section configured to perform a sample-and-hold operation on a digital input signal, the sample-and-hold operation driven by a clock signal;
• and
• a level determining section configured to:
• output a held sample at a first level when a level of the digital input signal is constant between sampling points;
• and
• output the held sample at a second level when the level of the digital input signal changes between sampling points.