Circuit and method for detecting skew of transistor in semiconductor device
AssigneeElectronics and Telecommunications Research Institute
InventorsHwang Hur, Jun-Gi Choi
Life of this patent
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Abstract
A circuit and method for easily detecting skew of a transistor within a semiconductor device are provided. The circuit for detecting the skew of the transistor includes a linear voltage generating unit for outputting a linear voltage by using a first supply voltage, a first attenuation unit for reducing variation width of the linear voltage according to the performance of the transistor, a saturation voltage generating unit for outputting a saturation voltage by using a second supply voltage, and a comparison unit for comparing an output of the first attenuation unit and the saturation voltage.
Claims16
1-14. (canceled)
A circuit for detecting skew of a transistors, the circuit comprising:
- a linear voltage generating unit including the transistors under test for outputting a linear voltage by using a first supply voltage;
- a first attenuation unit for reducing voltage level variation of the linear voltage according to the performance of the transistors;
- a saturation voltage generating unit for outputting a saturation voltage by using a second supply voltage whose level is higher than that of the first supply voltage;
- a voltage adjusting unit for adjusting an output of the first attenuation unit to a certain voltage level so as to easily compare said output with the saturation voltage;
- and
- a comparison unit for comparing an output of the voltage adjusting unit and the saturation voltage.
The circuit as recited in claim 22, wherein the linear voltage generating unit includes:
- the first switching device having a drain coupled with the first supply voltage and a gate receiving the second supply voltage;
- and
- the second switching device having a drain connected to a source of the first switching device, a gate receiving the first supply voltage and a source coupled with a third supply voltage.
A method for detecting skew of transistors under test, the method comprising:
- generating a linear voltage by using a first supply voltage;
- reducing voltage level variation of the linear voltage according to the performance of the transistors, thereby outputting an attenuated linear voltage;
- producing a saturation voltage by using a second supply voltage;
- and
- comparing the attenuated linear voltage and the saturation voltage.
The circuit as recited in claim 25, wherein the saturation voltage generating unit includes:
- a first switching device having a drain coupled with the second supply voltage and a gate receiving the second supply voltage;
- and
- a second switching device having a drain connected to a source of the first switching device, a gate receiving the first supply voltage and a source coupled with a third supply voltage.
Dependencies are inferred from the claim text.