Test apparatus for determining performance degradation

A testing apparatus, comprising:

• a stress application circuit that includes an operational amplifier, where an output terminal is connected to the gate of the transistor to be tested, a negative input terminal is connected to the source of the transistor to be tested, and a positive input terminal is connected to the output of a gate power source;
• a resistor that is connected between the negative input terminal and a negative power source and causes flow, into the resistor, of the drain current flowing in the transistor to be tested, and a drain power source that supplies predetermined drain voltage to the drain of the transistor to be tested;
• and
• measuring means that is connected to each of the drain, source, and gate terminals of the transistor to be tested and measures the electrical characteristics of the transistor to be tested, wherein
• the apparatus applies stress where the drain current flowing in the transistor to be tested is maintained at a constant value and detects the characteristic changes of the transistor to be tested in response to the stress, by supplying to the positive input terminal of the operational amplifier a gate command, obtained when target drain current flows in the resistor, by causing flow of predetermined drain current to the transistor to be tested, and detecting a measurement value of the measuring means,
• the apparatus is provided with monitoring means for monitoring the voltage of each terminal of the transistor to be tested when the drain current is caused to flow in the transistor to be tested by the stress application circuit,
• switches are provided between the respective terminals of the stress application circuit and the transistor to be tested as well as between the respective terminals of the measuring means and the transistor to be tested, and
• computer software for controlling the switches, the gate power source, the drain power source, and the monitoring means.