Structure of test area for a semiconductor tester
AssigneeKing Yuan Electronics Co., Ltd.
InventorsLin Yuan-Chi, Chih-Hung Hsieh, Shih-Fang Lin, Hao-Hsin Pan
Life of this patent
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Abstract
Devices and methods for DC and SLT (system level test) integration are disclosed. The DC circuit and the SLT circuit are integrated into the same device. Therefore, the DUT (device under testing) can precede the SLT before the FT (final test) when the DUT passes the DC.
Claims21
A structure of test area for a semiconductor tester, wherein the structure of test area comprises at least one test unit and the test unit comprising:
- a socket;
- a circuit board having a first circuit and a second circuit;
- and
- a switch element executing a switching motion according to a message of the semiconductor tester for making the socket electrically connect the first circuit or the second circuit.
A method for DC test and SLT integration of semiconductor tester, comprising:
- providing at least one test unit;
- providing at least one DUT (Device Under Test) and coupling the DUT with the test unit;
- executing the DC test;
- checking the result of the DC test and carrying a decision out;
- driving a switch element for making the DUT electrically connect the SLT circuit which is on the test unit;
- executing the SLT;
- and
- recording the result of the test and binning the DUT.
A semiconductor tester having a tester, a handler, an input/output port of an element under test and a test area, wherein the test area further comprises a plurality of test units, and the test unit comprises:
- a socket;
- a circuit board having a DC test circuit and a SLT circuit;
- and
- a switch element executing a switching motion by a message of the semiconductor tester for making the socket electrically connect the DC test circuit or the SLT circuit.
A semiconductor tester having a tester, a handler, an input/output port of an element under test and a test area, wherein the test area further comprises a plurality of test units, and the test unit comprises:
- a first socket;
- a DC test circuit electrically connecting the first socket;
- a second socket;
- a SLT circuit electrically connecting the second socket;
- wherein a DUT is sucked by the sorter and then inserted into one of the first socket and the second socket according to the sequence messages of the tester.
A structure of test area for a semiconductor tester comprising at least one test unit, wherein the test unit comprises:
- a socket;
- a circuit board having a DC test circuit and a SLT circuit;
- and
- a switch element executing a switching motion by a message of the semiconductor tester for making the socket electrically connect the DC test circuit or the SLT circuit.
Dependencies are inferred from the claim text.