US 2008/0174290 A1Published application

Voltage generation circuit

AssigneeKabushiki Kaisha Toshiba

InventorsRyu OGIWARA, Daisaburo TAKASHIMA

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Abstract

According to an aspect of the present invention, there is provided a voltage generation circuit including: first and second reference terminals to output first and second reference voltages, respectively; first PMOS and first NMOS transistors connected between high and low level power supply lines in series; an output terminal connected between the first PMOS and first NMOS transistors; a first operational amplifier including: first input terminals each including a gate of a PMOS transistor to be connected to one of the second reference terminal and the output terminal, and a first output terminal connected to the first PMOS transistor; and a second operational amplifier including: second input terminals each including a gate of an NMOS transistor to be connected to one of the first reference terminal and the output terminal, and a second output terminal connected to the first NMOS transistor.

Claims19

Dependent claims

A voltage generation circuit comprising:

a reference voltage generation circuit comprising:
a first reference terminal from which a first reference voltage is output, and
a second reference terminal from which a second reference voltage lower than the first reference voltage is output;
an output circuit comprising:
an output terminal from which an output voltage is output,
a first PMOS transistor connected between a first power supply line of a high level and the output terminal, and
a first NMOS transistor connected between the output terminal and a second power supply line of a low level;
a first operational amplifier comprising:
a first inverting input terminal comprising a gate of a PMOS transistor to be connected to the second reference terminal,
a first non-inverting input terminal comprising a gate of a PMOS transistor to be connected to the output terminal, and
a first output terminal connected to a gate of the first PMOS transistor;
and
a second operational amplifier comprising:
a second inverting input terminal comprising a gate of an NMOS transistor to be connected to the first reference terminal,
a second non-inverting input terminal comprising a gate of an NMOS transistor to be connected to the output terminal, and
a second output terminal connected to a gate of the first NMOS transistor.

13 more elements

A voltage generation circuit comprising:

a reference voltage generation circuit comprising:
a first reference terminal from which a first reference voltage is output, and
a second reference terminal from which a second reference voltage lower than the first reference voltage is output;
an output circuit comprising:
an output terminal from which an output voltage is output,
a first PMOS transistor connected between a first power supply line of a high level and the output terminal, and
a first NMOS transistor connected between the output terminal and a second power supply line of a low level;
a first operational amplifier comprising:
a first inverting input terminal comprising a gate of a PMOS transistor to be connected to the output terminal,
a first non-inverting input terminal comprising a gate of a PMOS transistor to be connected to the second reference terminal, and
a first output terminal that outputs a first control signal;
a second operational amplifier comprising:
a second inverting input terminal comprising a gate of an NMOS transistor to be connected to the output terminal,
a second non-inverting input terminal comprising a gate of an NMOS transistor to be connected to the first reference terminal, and
a second output terminal that outputs a second control signal;
a first inverting amplifier comprising:
a first control input terminal that is connected to the first output terminal and that receives the first control signal, and
a first control output terminal that is connected to the gate of the first PMOS transistor and that sends a third control signal that is obtained by inverting the first control signal;
and
a second inverting amplifier comprising:
a second control input terminal that is connected to the second output terminal and that receives the second control signal, and
a second control output terminal that is connected to the gate of the first NMOS transistor and that sends a fourth control signal that is obtained by inverting the second control signal.

19 more elements

Dependencies are inferred from the claim text.