Chip package reducing wiring layers on substrate and its carrier
AssigneeChipMOS Technologies Inc.
InventorsHung-Tsun Lin, Wu-Chang Tu, Cheng-Ting Wu
Life of this patent
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AssigneeChipMOS Technologies Inc.
InventorsHung-Tsun Lin, Wu-Chang Tu, Cheng-Ting Wu
Estimating the term…
An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.
An IC package comprising:
The chip carrier of an IC package comprising:
Dependencies are inferred from the claim text.