Semiconductor device using wiring substrate having a wiring structure reducing wiring disconnection

A semiconductor device, comprising:

• a wiring substrate;
• a semiconductor chip making flip chip connection to the wiring substrate;
• under-filling resin with which a gap between the wiring substrate and the semiconductor chip is filled up;
• a heat spreader adhered to the semiconductor chip;
• a power supply pattern and a wiring layer under surface via land which are formed on the wiring substrate and spaced out each other by a clearance region;
• an insulating film which covers the power supply pattern and the wiring layer under surface via land;
• a wiring layer via land formed on the insulating film;
• a via which penetrates the insulating film and connects the wiring layer under surface via land to the wiring layer via land;
• and
• a wiring which is formed on the insulating film, passes over the clearance region, and connects the wiring layer via land to the semiconductor chip;
• wherein
• the wiring layer via land is formed outside the semiconductor chip, and within a region of 1 mm width from an extension line of a diagonal line of the semiconductor chip;
• and
• the wiring is bent at a location 0.2 mm or less away from a boundary with the wiring layer via land.

A semiconductor device, comprising:

• a wiring substrate;
• a semiconductor chip making flip chip connection to the wiring substrate;
• under-filling resin with which a gap between the wiring substrate and the semiconductor chip is filled up;
• a heat spreader adhered to the semiconductor chip;
• a power supply pattern and a wiring layer under surface via land which are formed on the wiring substrate and spaced out each other by a clearance region;
• an insulating film which covers the power supply pattern and the wiring layer under surface via land;
• a wiring layer via land formed on the insulating film;
• a via which penetrates the insulating film and connects the wiring layer under surface via land to the wiring layer via land;
• and
• a wiring which is formed on the insulating film, passes over the clearance region, and connects the wiring layer via land to the semiconductor chip;
• wherein
• the wiring layer via land is formed outside the semiconductor chip, and within a region of 1 mm width from an extension line of a diagonal line of the semiconductor chip;
• and
• a width of the wiring over the clearance region is larger than a width of the thinnest portion in the wiring.

A manufacturing method of a semiconductor device, comprising the steps of:

• forming a wiring over a wiring substrate, covering an upper part of the wiring substrate by solder resist, and forming an opening in the solder resist so that the wiring may be exposed;
• and
• making flip chip connection of a semiconductor chip to the wiring substrate by connecting the wiring of the wiring substrate to an electrode of the semiconductor chip via a solder bump;
• wherein an amount of the solder bump's solder is made smaller than a volume of a sphere inscribed on a corner of the opening of the solder resist and on the electrode.