Stress relieving layer for flip chip packaging

A method for fabricating a semiconductor package, comprising:

• providing a semiconductor chip having a plurality of exposed conductive layers thereon;
• providing a first substrate having a first surface and a second surface;
• forming a plurality of through wafer vias under the first surface of the first substrate;
• filling the through wafer vias with a conductive material to form via plugs;
• bonding the semiconductor chip to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the via plugs;
• removing a portion of the second surface of the first substrate to expose the opposite ends of the via plugs;
• forming a plurality of UBM layers on the surfaces of the opposite ends of the via plugs;
• forming a plurality of solder bumps mounted on the UBM layers;
• and
• providing a second substrate having a first surface and a second surface, the solder bumps mounted to the first surface of the second substrate.

A semiconductor package structure, comprising:

• a semiconductor chip having a plurality of exposed conductive layers thereon;
• a first substrate having a plurality of through wafer vias with plugs filled therein, wherein a first side of the first substrate has the via plugs exposed and a second side has the opposite end of the via plugs exposed, and further wherein the chip is bonded to the first substrate, wherein the conductive layers are aligned and in contact with the via plugs of the first side;
• a plurality of UBM layers mounted to the opposite ends of the via plugs;
• a plurality of solder bumps mounted on the UBM layers;
• and
• a second substrate having a first surface and a second surface, the solder bumps mounted to the first surface of the second substrate.