Chip carrier substrate capacitor and method for fabrication thereof
AssigneeInternational Business Machines Corporation
InventorsPaul S. Andry, Chirag S. Patel
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Abstract
A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.
Claims20
A chip carrier substrate comprising:
- a substrate including a capacitor aperture located within the substrate laterally separated from a via aperture located through the substrate;
- and
- a capacitor located within the capacitor aperture and a via located within the via aperture, where the capacitor aperture has narrower linewidth than the via aperture.
A method for fabricating a chip carrier substrate comprising:
- forming simultaneously a capacitor aperture laterally separated from a via aperture within a substrate;
- and
- forming a capacitor within the capacitor aperture and a via within the via aperture.
A method for fabricating a chip carrier substrate comprising:
- forming simultaneously a capacitor aperture laterally separated from a via aperture within a substrate, the capacitor aperture being formed simultaneously of narrower linewidth and shallower depth than the via aperture;
- and
- forming a capacitor within the capacitor aperture and a via within the via aperture.
Dependencies are inferred from the claim text.