Air gap under on-chip passive device

A method of fabricating a microelectronic chip, comprising:

• forming a plurality of front-end-of-line (“FEOL”) devices in a semiconductor region of the microelectronic chip;
• forming an interlevel dielectric region (“ILD”) overlying the plurality of FEOL devices, the ILD being resistant to attack by a first etchant which attacks the semiconductor region;
• forming a passive device overlying the ILD region;
• and
• using the first etchant, removing a portion of the semiconductor region directly underlying the passive device to form an air gap underlying the passive device.

A method of fabricating a microelectronic chip, comprising:

• forming a plurality of front-end-of-line (“FEOL”) devices in a semiconductor region of the microelectronic chip;
• forming a plurality of stacked interlevel dielectric regions (“ILDs”) overlying the plurality of FEOL devices, the plurality of stacked ILDs including a first ILD layer and a second ILD layer, the second ILD layer being etch-resistant to a first etchant which attacks the first ILD layer;
• using the first etchant, removing a portion of the first ILD layer to provide an air gap underlying the second ILD layer;
• and
• forming a passive device overlying the plurality of stacked ILDs, such that the air gap directly underlies the passive device.

A microelectronic chip, comprising:

• an inductor supported partially by a dielectric region of a substrate, the substrate including a single-crystal semiconductor region underlying the inductor;
• a cavity underlying at least some conductors of the inductor in registration with the at least some conductors;
• and
• a dielectric layer overlying and hermetically sealing the at least some conductors and the cavity.