Semiconductor device and method for fabricating the same
AssigneePanasonic Corporation
InventorSusumu Akamatsu
Life of this patent
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Abstract
A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape, and each of the second MIS transistors includes second L-shaped sidewalls each having an L-shaped cross-sectional shape and outer sidewalls. The minimum thickness of a part of the liner insulating film located on each of second source/drain regions of the second MIS transistor is larger than the minimum thickness of a part thereof located on each of first source/drain regions of the first MIS transistor.
Claims35
A semiconductor device comprising:
- a first MIS transistor including:
- a first gate insulating film formed on a first area of a semiconductor substrate;
- a first gate electrode formed on the first gate insulating film;
- first L-shaped sidewalls covering both sides of the first gate electrode and part of the semiconductor substrate to each have an L-shaped cross-sectional shape;
- and
- first source/drain regions formed on both sides of a part of the first area covered with the first gate electrode and the first L-shaped sidewalls;
- a second MIS transistor including:
- a second gate insulating film formed on a second area of the semiconductor substrate;
- a second gate electrode formed on the second gate insulating film;
- second L-shaped sidewalls covering both sides of the first gate electrode and part of the semiconductor substrate to each have an L-shaped cross-sectional shape;
- outer sidewalls formed on the second L-shaped sidewalls;
- and
- second source/drain regions formed on both sides of a part of the second area covered with the second gate electrode, the second L-shaped sidewalls and the outer sidewalls;
- and
- a liner insulating film covering the first MIS transistor and the second MIS transistor and applying stress to a channel region of the first MIS transistor along the gate length direction of the first gate electrode,
- wherein no outer sidewall is formed on the first L-shaped sidewalls, and the minimum thickness of a part of the liner insulating film located on each of the second source/drain regions is larger than the minimum thickness of a part of the liner insulating film located on each of the first source/drain regions.
A method for fabricating a semiconductor device comprising a first MIS transistor formed on a first area of a semiconductor substrate and a second MIS transistor formed on a second area of the semiconductor substrate, the method comprising the steps of:
- (a) forming a first gate insulating film and a first gate electrode on the first area and forming a second gate insulating film and a second gate electrode on the second area;
- (b) forming first sidewalls and second sidewalls in the order away from the first gate electrode to cover both sides of the first gate electrode and forming third sidewalls and fourth sidewalls in the order away from the second gate electrode to cover both sides of the second gate electrode;
- (c) forming first source/drain regions on both sides of a part of the first area covered with the first gate electrode, the first sidewalls and the second sidewalls;
- (d) forming second source/drain regions on both sides of a part of the second area covered with the second gate electrode, the third sidewalls and the fourth sidewalls;
- (e) after the steps (c) and (d), removing the second sidewalls;
- and
- (f) after the step (e), forming a liner insulating film to cover the first gate electrode, the first sidewalls, the first source/drain regions, the second gate electrode, the third sidewalls, the fourth sidewalls, and the second source/drain regions, the liner insulating film applying stress to a channel region of the first MIS transistor along the gate length direction of the first gate electrode,
- wherein in the step (f), the liner insulating film is formed such that the minimum thickness of a part of the liner insulating film located on each of the second source/drain regions becomes larger than the minimum thickness of a part of the liner insulating film located on each of the first source/drain regions.
Dependencies are inferred from the claim text.