Hybrid process for forming metal gates

A semiconductor structure comprising:

• a semiconductor substrate;
• an NMOS device comprising:
• a first gate dielectric on the semiconductor substrate;
• a first metal-containing gate electrode layer over the first gate dielectric;
• a polysilicon layer over the first metal-containing gate electrode layer;
• a silicide region on the polysilicon layer;
• and
• a first contact etch stop layer having a portion on the silicide region and physically contacting the silicide region;
• and
• a PMOS device comprising:
• a second gate dielectric on the semiconductor substrate;
• a second metal-containing gate electrode layer over the second gate dielectric, wherein the first metal-containing gate electrode layer has a first work function different from a second work function of the second metal-containing gate electrode layer;
• and
• a second contact etch stop layer having a portion on the second metal-containing gate electrode layer and physically contacting the second metal-containing gate electrode layer.

A semiconductor structure comprising:

• a semiconductor substrate;
• a first MOS device of a first conductivity type, the first MOS device comprising:
• a first gate dielectric on the semiconductor substrate;
• a first metal-containing gate electrode layer over the first gate dielectric;
• a first etch stop layer having a first portion over the first metal-containing gate electrode layer;
• and
• a first region between the first portion of the first contact etch stop layer and the first metal-containing gate electrode layer;
• and
• a second MOS device of a second conductivity type opposite the first conductivity type, the second MOS device comprising:
• a second gate dielectric on the semiconductor substrate;
• a second metal-containing gate electrode layer over the second gate dielectric;
• a second contact etch stop layer having a second portion over the second metal-containing gate electrode layer, and
• a second region between the second metal-containing gate electrode layer and the second portion of the second contact etch stop layer, wherein the first region comprises more silicon than the second region.