Method of forming high voltage semiconductor device and the high voltage semiconductor device using the same
AssigneeSamsung Electronics Co., Ltd.
InventorMi-Hyun Kang
Life of this patent
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Abstract
A method of forming a high voltage semiconductor device includes forming a thermal oxide layer on a semiconductor substrate where a trench is formed, forming a chemical vapor deposition (CVD) oxide layer on the thermal oxide layer, and etching the CVD oxide layer and the thermal oxide layer at different etching selectivities to form a gate insulating layer having an inclined sidewall and a device isolation pattern. Thus, a gate insulating layer having a sufficiently large thickness and a device isolation pattern can be formed simultaneously by means of simple process steps and degradation of the device can be suppressed even when a high voltage is applied.
Claims18
A method of forming a high voltage semiconductor device, comprising:
- thermally oxidizing a semiconductor substrate to form a thermal oxide layer;
- uniformly forming a chemical vapor deposition (CVD) oxide layer on the thermal oxide layer;
- forming a gate mask pattern on the CVD oxide layer;
- etching the CVD oxide layer and the thermal oxide layer using the gate mask pattern at a different etch rate to expose a portion of the semiconductor substrate, thereby forming a gate insulating layer having an inclined sidewall;
- and
- forming a gate electrode on the gate insulating layer.
A high voltage semiconductor device, comprising:
- a semiconductor substrate including a buried insulating layer and a semiconductor layer;
- a gate insulating layer having a bottom surface that is even with a flat top surface of the semiconductor substrate and including a thermal oxide layer pattern and a CVD oxide layer pattern that are stacked sequentially, wherein a sidewall of the gate insulating layer is inclined;
- and
- a gate electrode formed on the gate insulating layer.
Dependencies are inferred from the claim text.