Semiconductor memory devices including vertically oriented transistors and methods of manufacturing such devices

A method of manufacturing a semiconductor device, comprising:

• forming a first active pattern having a mesa structure with a transverse cross-section of non-uniform width on a substrate;
• forming a second active pattern that has a pillar structure on the first active pattern;
• and
• forming a gate surrounding a sidewall of the second active pattern that defines a channel through the second active pattern.

A semiconductor device comprising:

• fin active patterns including upper portions and lower portions, the fin active patterns extending along a predetermined direction and being parallel to each other, wherein a transverse cross-section of each of the fin active patterns has a non-uniform width;
• bit lines in the fin active patterns;
• pillar active patterns on the fin active patterns, the pillar active patterns being separated from each other by a predetermined distance;
• and
• gates surrounding the pillar active patterns to form a channel through each of the pillar active patterns, wherein each channel is oriented substantially perpendicular to a major axis of its respective pillar active pattern.

A method of manufacturing a semiconductor device, comprising:

• patterning a substrate to form pillar active patterns;
• forming impurity regions at portions of the substrate adjacent to the pillar active patterns;
• forming gates on sidewalls of the pillar active patterns, wherein each gate surrounds the sidewall of a respective one of the pillar active patterns;
• forming masks on the pillar active patterns and the gates, wherein the masks extend along a predetermined direction and are parallel to each other;
• and
• etching the substrate using the masks to form bit lines and fin active patterns, wherein each of the bit lines has a non-planar sidewall.

A semiconductor device, comprising:

• a first active pattern extending from an upper surface of a semiconductor substrate;
• a first impurity-doped region in an upper portion of the fin active pattern, the first impurity-doped region having a sidewall that is at least partly curved;
• and
• a second active pattern on an upper surface of the first active pattern, the second active pattern including a gate pattern encircling at least one side surface of the second active pattern, a second impurity-doped region in an upper portion of the second active pattern, and a channel extending between the first impurity-doped region and the second impurity-doped region such that the channel is oriented substantially perpendicular to the upper surface of the semiconductor substrate.