Access device having vertical channel and related semiconductor device and a method of fabricating the access device
AssigneeSamsung Electronics Co., Ltd.
InventorsJae-Man YOON, Yong-Chul OH, Hui-Jung KIM, Hyun-Woo CHUNG
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Abstract
An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.
Claims24
An access device adapted for use in a semiconductor device and comprising:
- a vertically oriented channel separating a lower source/drain region and an upper source/drain region;
- a gate dielectric disposed on the channel;
- a unified gate electrode/connection line coupled to the channel across the gate dielectric,
- wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.
A semiconductor device, comprising:
- adjacent first and second access devices disposed on a substrate, each first and second access device comprising a vertically oriented channel separating a lower source/drain region and an upper source/drain region, and a gate dielectric disposed on the channel;
- a first interlayer insulating layer disposed on the substrate and separating the first and second access devices;
- and
- a unified gate electrode/connection line disposed on the first interlayer insulating layer and coupled to the channel of the first and second access devices, wherein the unified gate electrode/connection line comprises descending lip portions, each descending lip portion being disposed proximate to the gate dielectric of the first access device or the second access device and overlaying at least a portion of a lower source/drain region associated with the first access device or the second access device.
A memory system comprising:
- a memory controller connected to and controlling operation of a memory, the memory comprising a memory cell region, the memory cell region comprising an array of memory cells, each memory cell in the array comprising an access element and a storage element, wherein each access element comprises:
- a vertically oriented channel separating a lower source/drain region and an upper source/drain region;
- a gate dielectric disposed on the channel;
- a unified gate electrode/word line coupled to the channel across the gate dielectric, wherein the unified gate electrode/word line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.
A method of fabricating an access device, comprising:
- forming a vertical pillar extending from a semiconductor substrate;
- forming a gate dielectric on sidewalls of the vertical pillar;
- using a sacrificial gate spacer formed on the gate dielectric to form a self-aligned lower source/drain region;
- and thereafter,
- replacing the sacrificial gate spacer with a unified gate electrode/connection line.
Dependencies are inferred from the claim text.