US 2008/0173933 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

The semiconductor device includes a substrate having a conductive layer formed on its surface. The conductive layer has a columnar semiconductor formed thereon. The columnar semiconductor has an insulating layer formed therearound. The insulating layer has an electrode film formed therearound. The electrode film functions as an gate electrode of a transistor. The electrode film includes an laminate of two or more conductive films having different work functions.

Claims11

Dependent claims

A semiconductor device comprising:

a substrate having a conductive layer formed on its surface;
a columnar semiconductor formed on the conductive layer;
an insulating layer formed around the columnar semiconductor;
and
an electrode film formed around the insulating layer, the electrode film functioning as a gate electrode of a transistor,
the electrode film comprising an laminate of two or more conductive films having different work functions.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/013,672Filed 14 Jan 2008

Priority

JP 2007-00618315 Jan 2007

Published

24 Jul 2008

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Facts

Application

12/013,672Filed 14 Jan 2008

Priority

JP 2007-00618315 Jan 2007

Published

24 Jul 2008

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Semiconductor memory device

Life of this patent

Abstract

Claims11

Semiconductor memory device

Life of this patent

Abstract

Claims11