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AssigneeMacronix International Co., Ltd.
InventorsChiaHua Ho, Erh-Kun Lai
Estimating the term…
The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.
A memory structure having multiple memory layers, comprising:
A memory structure having multiple memory layers, comprising:
A memory structure having multiple memory layers, comprising:
A method for manufacturing a memory device, comprising:
Dependencies are inferred from the claim text.