Electronic device including fins and discontinuous storage elements and processes of forming and using the same

A process of forming an electronic device comprising:

• forming a first trench and a second trench within a substrate, wherein a portion of the substrate lies between the first trench and the second trench, and has a width of no more than approximately 90 nm;
• forming discontinuous storage elements within the first trench and the second trench;
• forming a first gate electrode within the first trench and a second gate electrode within the second trench;
• and
• removing a portion of the discontinuous storage elements to form a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and the portion of the substrate, and the second set of the discontinuous storage elements lies between the second gate electrode and the portion of the substrate.

A process of using an electronic device comprising:

• providing a memory cell including:
• a substrate, wherein a first trench and a second trench extend therein and are spaced apart from each other by a portion of the substrate;
• a first gate electrode within the first trench;
• a first source/drain region lying along a first bottom of the first trench, wherein the first source/drain region is coupled to a first bit line;
• a second gate electrode within the second trench;
• a second source/drain region lying along a second bottom of the second trench, wherein the first source/drain region is coupled to a second bit line;
• and
• discontinuous storage elements including a first set of discontinuous storage elements and a second set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between the first gate electrode and a first bottom of the first trench, and the second set of the discontinuous storage elements lies between the second gate electrode and a second bottom of the second trench;
• and
• programming a first bit of the memory cell comprising:
• biasing the first bit line and the second bit line at a first voltage difference;
• biasing the first gate electrode, such that a second voltage difference between the first gate electrode and the first bit line is no greater than approximately half of the first voltage difference;
• and
• biasing the second gate electrode, such that a third voltage difference between the second gate electrode and the first bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference, wherein a substantial fraction of current flows underneath the portion of the substrate during programming the first bit.