Electronic device including trenches and discontinuous storage elements and processes of forming and using the same

A process of forming an electronic device comprising:

• providing a substrate having a primary surface;
• forming a patterned sacrificial layer over the primary surface of the substrate;
• forming a trench extending from the primary surface of the substrate, wherein the trench has a first wall and a bottom;
• forming discontinuous storage elements over the primary surface and within the trench;
• forming a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, wherein a portion of the first gate electrode lies at an elevation higher than the primary surface and adjacent to the patterned sacrificial layer;
• removing the patterned sacrificial layer after forming the first gate electrode;
• forming a second gate electrode outside the trench and adjacent to the first gate electrode, wherein forming the second gate electrode is performed after removing the patterned sacrificial layer;
• and
• removing a portion of the discontinuous storage elements to form a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench.

A process of using an electronic device comprising:

• providing a memory cell including:
• a substrate including a trench having a bottom and a first wall;
• a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench;
• a second gate electrode overlying the substrate outside of the trench;
• a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench;
• a first source/drain region adjacent to the third gate electrode and coupled to a first bit line;
• a second source/drain region adjacent to the second gate electrode and coupled to a second bit line;
• and
• discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench;
• and
• programming a first bit of the memory cell comprising:
• biasing the first bit line and the second bit line at a first voltage difference;
• biasing the third gate electrode, such that a second voltage difference between the third gate electrode and the first bit line is no greater than approximately half of the first voltage difference;
• biasing the first gate electrode, such that a third voltage difference between the first gate electrode and the first bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference;
• and
• biasing the second gate electrode, such that a fourth voltage difference between the second gate electrode and the first bit line is in a range of approximately 0.5 to approximately 1.5 times the first voltage difference.