Memory having a vertical access device
AssigneeMicron Technology, Inc.
InventorWerner Juengiing
Life of this patent
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Abstract
Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the opposed side walls. A dielectric layer may be deposited on the side walls and the floor of the recess. A conductive film may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.
Claims65
A method of forming a memory device structure for a memory device, comprising:
- providing a recess in a substrate having a pair of opposed side walls and a floor extending between the opposed side walls;
- depositing a dielectric layer to the side walls and the floor of the recess;
- forming a conductive film on the dielectric layer;
- and
- processing the conductive film to remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.
A memory device structure, comprising:
- a recess formed in a semiconductor substrate that includes a pair of opposing side walls, the side walls including active regions having a selected conductivity;
- a conductive film structure at least partially disposed on respective side walls of the recess;
- and
- a dielectric layer interposed between the active regions and the conductive film structure.
The memory device structure of 15, further comprising a floor positioned between the pair of opposing side walls, wherein the dielectric layer further comprises a trench dielectric layer that substantially covers the floor and the pair of opposing side walls.
A memory device, comprising:
- at least one peripheral circuit positioned on a semiconductor substrate;
- and
- a memory array formed on the substrate and operably coupled to the at least one peripheral circuit, the memory array including at least one vertical access device, further comprising:
- a recess formed in the semiconductor substrate that includes a pair of opposing side walls, the side walls including active regions of the vertical access device having a selected conductivity;
- a conductive film structure at least partially disposed on respective side walls of the recess proximate to the active regions;
- and
- a dielectric layer interposed between the active regions and the conductive film structure.
A memory array for a memory device, comprising:
- a plurality of memory cells formed on a semiconductor substrate and coupled to word lines and generally perpendicular bit lines formed on the substrate, each memory cell further comprising:
- a storage device;
- and
- an access device formed in the substrate that is coupled to the storage device and to a selected one of the word lines and a selected one of the bit lines, the array further comprising:
- a recess formed in the semiconductor substrate that includes a pair of opposing side walls and a floor extending there between, the side walls including active regions of the access device having a selected conductivities;
- a conductive film structure at least partially disposed on respective side walls of the recess;
- and
- a dielectric layer interposed between the active regions and the conductive film structure.
A processing system, comprising:
- a central processing unit (CPU);
- and
- a memory device operably coupled to the CPU by a communications bus, the memory device including at least one access device, further comprising:
- a recess that extends into a semiconductor substrate that includes a pair of opposing side walls and a floor extending there between, the side walls including active regions of the access device formed therein;
- a conductive film structure at least partially disposed on respective side walls of the recess;
- and
- a dielectric layer interposed between the active regions and the conductive film structure.
A memory array for a memory device, comprising:
- a plurality of memory cells formed on a semiconductor substrate and coupled to word lines and generally perpendicular bit lines formed on the substrate, each memory cell further comprising:
- a plurality of storage devices;
- and
- a plurality of access devices formed in the substrate that are operably coupled to the storage device and to a selected one of the word lines and a selected one of the bit lines, the array further comprising:
- a recess formed in the semiconductor substrate that extends between the access devices and includes a pair of opposing side walls and a floor extending there between, wherein the side walls include active regions of the access devices;
- a conductive film structure at least partially disposed on respective side walls of the recess;
- and
- a dielectric layer interposed between the active regions and the conductive film structure.
Dependencies are inferred from the claim text.