Semiconductor memory device and write method of the same
AssigneeKabushiki Kaisha Toshiba
InventorKiyohito NISHIHARA
Life of this patent
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Abstract
A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween. A capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.
Claims18
A write and erase method of a semiconductor memory device comprising a floating gate type transistor having:
- a semiconductor substrate;
- a gate insulating film formed on the semiconductor substrate;
- a floating gate electrode formed on the gate insulating film;
- and
- a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween,
- wherein a capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.
A semiconductor memory device comprising a floating gate type transistor having:
- a semiconductor substrate;
- a gate insulating film formed on the semiconductor substrate;
- a floating gate electrode formed on the gate insulating film;
- and
- a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween,
- wherein a capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.
A semiconductor memory device comprising:
- a semiconductor substrate;
- an insulating layer formed on the semiconductor substrate;
- an SOI layer formed on the insulating layer;
- a first gate insulating film formed on an upper surface of the SOI layer;
- a floating gate electrode formed on the first gate insulating film;
- a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween;
- a second gate insulating film formed on a lower surface of the SOI layer;
- a back gate electrode formed below the floating gate electrode so as to sandwich the second gate insulating film, and
- a diffusion layer formed in the SOI layer between the back gate electrode and the floating gate electrode.
Dependencies are inferred from the claim text.