Solid-state imaging device having wiring layer which includes lamination of silicide layer in order to reduce wiring resistance, and manufacturing method for the same

A manufacturing method for a solid-state imaging device, comprising:

• (a) a signal charge accumulator forming step of performing, on a semiconductor substrate, formation of a signal charge accumulator which accumulates a signal charge generated by a photoelectric conversion;
• (b) a transistor forming step of performing, on the semiconductor substrate, formation of (i) a transmission transistor adjacent to the signal charge accumulator and (ii) a reset transistor, a source of which is connected to a drain of the transmission transistor;
• (c) a first insulating layer forming step of forming a first insulating layer so as to cover (i) a main surface of the semiconductor substrate, (ii) the transmission transistor, and (iii) the reset transistor;
• (d) a sidewall forming step of forming, by removing the first insulating layer by etching except for a region above the signal charge accumulator, a sidewall on a lateral surface of a gate of the transmission transistor and on both lateral surfaces of agate of the reset transistor, the lateral surface of the gate of the transmission transistor being on a drain side of the transmission transistor;
• (e) a second insulating layer forming step of forming a second insulating layer so as to cover (i) the main surface, (ii) the transmission transistor, and (iii) the reset transistor;
• (f) an opening forming step of forming, on the second insulating layer, an opening above the gate of the transmission transistor and above the gate and the drain of the reset transistor;
• and
• (g) a compound layer forming step of forming, through the openings, a compound layer composed of metal and a semiconductor on the gate of the transmission transistor and on the gate and the drain of the reset transistor.