Enhanced mobility cmos transistors with a v-shaped channel with self-alignment to shallow trench isolation

A semiconductor structure, comprising:

• a semiconductor substrate with a substrate orientation;
• a V-shaped groove with a ridge and a first crystallographic facet and a second crystallographic facet of a semiconductor material, wherein said first crystallographic facet and said second crystallographic facet are joined by said ridge;
• a frame of constant width of semiconductor surface, said frame surrounding said V-shaped groove and bounded by and self-aligned to shallow trench isolation;
• a channel located beneath said V-shaped groove, said channel adjoining a portion of said ridge, a portion of said first crystallographic facet, a portion of said second crystallographic facet, and at least one portion of said frame;
• a source adjoined to said channel and located on said ridge;
• a drain adjoined to said channel and not adjoined to said source and located on said ridge;
• a gate dielectric adjoined to and located above said channel;
• and
• a gate conductor adjoined to said gate dielectric and not adjoined to said channel, said source and said drain.

A method of fabricating a semiconductor structure, comprising:

• providing a semiconductor substrate with a substrate orientation;
• subjecting a portion of said semiconductor to at least one an etchant with an anisotropic etch rate along different crystallographic planes;
• forming at least two new facets which are joined with a V-shaped cross-sectional profile with surface orientations that are at an angle substantially greater than zero degree to said substrate orientation and is substantially not orthogonal to said substrate orientation;
• and
• forming a gate dielectric on said at least one facet.