Dynamic random access memory cell and manufacturing method thereof

A manufacturing method of a dynamic random access memory cell, the method comprising:

• forming a bottom oxide layer on a substrate;
• forming a first semiconductor layer on the bottom oxide layer and forming a second semiconductor layer on the first semiconductor layer;
• forming an electrode stack structure on the second semiconductor layer;
• patterning the electrode stack structure, the second semiconductor layer and the first semiconductor layer;
• forming an insulation layer at two sides of the first semiconductor layer, the insulation layer contacting at least part of the two sides of the second semiconductor layer, the height of the insulation layer greater than the height of the first semiconductor layer;
• and
• forming a doping layer on at least part of the two sides of the second semiconductor layer, wherein a top surface of the doping layer and a top surface of the second semiconductor layer are in the same horizontal plane.

A manufacturing method of a dynamic random access memory cell, the method comprising:

• forming a bottom oxide layer on a substrate;
• forming a first semiconductor layer on the bottom oxide layer and forming a second semiconductor layer on the first semiconductor layer;
• forming an electrode stack structure on the second semiconductor layer;
• patterning the electrode stack structure, the second semiconductor layer and the first semiconductor layer;
• forming an insulation layer at two sides of the first semiconductor layer and the second semiconductor layer, the height of the insulation layer greater than the height of the first semiconductor layer;
• and
• forming a doping layer on the insulation layer.

A manufacturing method of a dynamic random access memory cell, the method comprising:

• forming a bottom oxide layer on a substrate;
• forming a first semiconductor layer on the bottom oxide layer and forming a second semiconductor layer on the first semiconductor layer;
• forming an electrode stack structure on the second semiconductor layer;
• patterning the electrode stack structure, the second semiconductor layer and the first semiconductor layer;
• forming an insulation layer at two sides of the first semiconductor layer, the second semiconductor layer and the electrode stack structure;
• patterning the electrode stack structure again;
• and
• forming a doping layer on the second semiconductor layer, the doping layer located between two sides of the electrode stack structure and the insulation layer.