Data processing system and semiconductor integrated circuit

A semiconductor integrated circuit comprising, over one semiconductor substrate:

• a plurality of first processors of which a logical function is operable to be controlled variably;
• a second processor operable to control the first processors;
• and
• a plurality of third processors operable to issue a data processing request to the second processor,
• wherein the first processor includes;
• a buffer memory operable to store logical configuration information received from the second processor;
• an arithmetic circuit of which a logical function is determined, upon receiving the logical configuration information stored in the buffer memory;
• a data memory coupled to the arithmetic circuit;
• and
• a control circuit, in response to a direction from the second processor, operable to control internal transfer of the logical configuration information from the buffer memory to the arithmetic circuit and internal transfer of data between the arithmetic circuit and the data memory,
• wherein the second processor controls assignment of a task to the first processor in response to the data processing request issued by the third processor, and
• wherein, when the first processor switches a task to process, the second processor performs cost calculation in consideration of amount of a transfer time of the logical configuration information and a data transfer time for switching the logical function to a task as a switching candidate with the same priority, and determines a task to be performed next based on the calculation result.

A data processing system comprising;

• a first processor;
• and
• a second processor operable to control assignment of a task to the first processor,
• wherein the first processor includes:
• an arithmetic circuit;
• a local memory operable to store information received from the second processor and an operation result by the arithmetic circuit;
• and
• a control circuit operable to control internal transfer of information between the local memory and the arithmetic circuit in response to a direction from the second processor, and
• wherein, when the first processor switches a task to process, the second processor performs cost calculation in consideration of amount of required transfer time of the information to a task as a switching candidate with the same priority, and determines a task to be performed next based on the calculation result.