Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for generating a clock-tree on an integrated circuit (IC) chip, the method comprising:

• receiving a placement for a chip layout, where the placement includes a set of registers at fixed locations in the chip layout;
• generating a timing criticality profile for the set of registers, wherein the timing criticality profile specifies timing criticalities between pairs of registers in the set of registers;
• and
• clustering the set of registers based on the timing criticality profile to create a clock-tree for the set of registers;
• wherein clustering registers based on the timing criticality profile facilitates using commonly-shared clock paths in the clock-tree to provide clock signals to timing critical register pairs.

A computer system that generates a clock-tree on an integrated circuit (IC) chip, comprising:

• a processor;
• a memory;
• a receiving mechanism configured to receive a placement for a chip layout, where the placement includes a set of registers in fixed locations in the chip layout;
• a generating mechanism configured to generate a timing criticality profile for the set of registers, wherein the timing criticality profile specifies timing criticalities between pairs of registers in the set of registers;
• and
• a clustering mechanism configured to cluster the set of registers based on the timing criticality profile to create a clock-tree for the set of registers;
• wherein clustering registers based on the timing criticality profile facilitates using commonly-shared clock paths in the clock-tree to provide clock signals to timing critical register pairs.