Method and apparatus for determining the timing of an integrated circuit design
AssigneeSynopsys, Inc.
InventorsYiu-Chung Mang, Pei-Hsin Ho
Life of this patent
Estimating the term…
Abstract
A system that determines the timing of an integrated circuit (IC) design is presented. During operation, the system receives a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design. Next, the system estimates capacitances for cells within the IC design based on analytic models of the cells. The system then estimates the post-physical-optimization timing of the IC design based on the netlist, the capacitances, and the analytic models, wherein the post-physical-optimization timing is estimated without performing physical optimization.
Claims29
A method for determining the timing of an integrated circuit (IC) design, comprising:
- receiving a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design;
- estimating capacitances for cells within the IC design based on analytic models of the cells;
- and
- estimating the post-physical-optimization timing of the IC design based on the netlist, the capacitances, and the analytic models, wherein the post-physical-optimization timing is estimated without performing physical optimization.
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for determining the timing of an integrated circuit (IC) design, wherein the method comprises:
- receiving a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design;
- estimating capacitances for cells within the IC design based on analytic models of the cells;
- and
- estimating the post-physical-optimization timing of the IC design based on the netlist, the capacitances, and the analytic models, wherein the post-physical-optimization timing is estimated without performing physical optimization.
An apparatus that determines the timing of an integrated circuit (IC) design, comprising:
- a receiving mechanism configured to receive a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design;
- a capacitance-estimation mechanism configured to estimate capacitances for cells within the IC design based on analytic models of the cells;
- and
- a timing-estimation mechanism configured to estimate the post-physical-optimization timing of the IC design based on the netlist, the capacitances, and the analytic models, wherein the post-physical-optimization timing is estimated without performing physical optimization.
Dependencies are inferred from the claim text.