Parity error detecting circuit and method
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Hun Lee, Jae-Youl Lee, Jong-Seon Kim, Kyung-Suc Nah
Life of this patent
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Abstract
A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.
Claims10
A parity error detecting circuit comprising:
- a first operation unit to receive a serial data signal and a first signal, perform a logic operation on the two received signals, and output a result of the logic operation as the first signal in response to a first clock signal;
- a shift register to shift the first signal in response to the first clock signal and output a second signal;
- and
- a second operation unit to receive the first signal and the second signal, perform a logic operation on the two received signals, and output a result of the logic operation in response to a second clock signal.
A parity error detecting circuit comprising:
- a first operation unit to receive a serial data signal and a first signal, perform a logic operation on the serial data signal and the first signal, and output a result of the logic operation as the first signal in response to a first clock signal;
- a second operation unit to output the first signal as a second signal in response to a second clock signal;
- and
- a third operation unit to receive the first signal and the second signal, perform a logic operation on the first and second signals, and output a result of the logic operation in response to a third clock signal.
A method of detecting parity error, comprising:
- receiving a serial data signal and a first signal;
- performing a first logic operation on the serial data signal and the first signal in response to a first clock signal to generate a second signal;
- shifting the second signal in response to the first clock signal to generate a third signal;
- and
- performing a second logic operation on the second signal and the third signal in response to a second clock signal to generate an output signal.
Dependencies are inferred from the claim text.