Area efficient on-the-fly error correction code (ECC) decoder architecture
AssigneeBroadcom Corporation, a California Corporation
InventorJohn P. Mead
Life of this patent
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AssigneeBroadcom Corporation, a California Corporation
InventorJohn P. Mead
Estimating the term…
Area efficient on-the-fly error correction code (ECC) decoder architecture. A novella means is presented by which only 2 banks of registers are employed (as opposed to 3 or more banks) when generating an error location polynomial in accordance with decoding of a Reed-Solomon (RS) coded signal. Berlekamp-Massey decoding processing can be employed when decoding such a RS coded signal. This approach provides for a significant amount of savings in hardware. For example, one embodiment designed in accordance with the invention is operable to implement an entire 12-bit (t=120) Reed-Solomon ECC system for HDD applications which consumes only approximately 170 k gates. Of these 170 k gates, 70K gates are attributed to the syndrome/symbol computer. Moreover, because of the pipelined arrangement of the decoding processing presented herein (which allows for more clock cycles to perform the division), division processing can be performed using an inverter and multiplier.
A decoder that is operable to employ Berlekamp-Massey decoding processing when decoding a Reed-Solomon (RS) coded signal, comprising:
A decoder that is operable to employ Berlekamp-Massey processing when decoding a Reed-Solomon (RS) coded signal, comprising:
A method that is operable to employ Berlekamp-Massey decoding processing when decoding a Reed-Solomon (RS) coded signal, the method comprising:
Dependencies are inferred from the claim text.