Memory including error correction code circuit

A memory comprising:

• an array of memory cells;
• read data lines for reading data from the array of memory cells;
• write data lines for writing data to the array of memory cells;
• and
• an error correction code circuit configured to receive external data to be written to the array of memory cells, combine the external data with data read from the array of memory cells, and encode the combined data for writing to the array of memory cells.

A memory comprising:

• an array of memory cells;
• means for simultaneously writing data to the array of memory cells and reading data from the array of memory cells;
• and
• means for encoding a data word including at least one byte from an external circuit and at least one byte from the array of memory cells.

A method for writing to a memory, the method comprising:

• receiving first external data from an external circuit;
• reading first data from a memory array through a first data path;
• combining the first external data with the first data read from the memory array;
• encoding the combined data;
• and
• writing the encoded combined data to the memory array through a second data path.

A method for accessing a memory, the method comprising:

• receiving a first portion of a data word from an external circuit;
• receiving a second portion of the data word from an array of memory cells;
• combining the first portion and the second portion to provide the data word;
• encoding the data word;
• and
• writing the encoded data word to the array of memory cells.